Principal Analog Design Engineer — High-Speed AI SerDes

Astera Labs; Irvine (CA); On-site; USD 170,000 - 210,000; Full time

Benefits offered by this job

Discretionary bonus

Competitive benefits

Job summary

Astera Labs is redefining AI connectivity in rack-scale infrastructure. The Principal Analog Design Engineer will own the design of high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O, shaping performance, power, and reliability in data centers.

You will lead from concept through silicon bring-up, mentor engineers, set technical standards, and collaborate with digital, physical design, and systems teams to deliver full-chip solutions for next-gen AI compute.

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 8+ years of analog/mixed-signal IC design experience.
• Proven track record designing high-speed analog circuits (PLLs, SerDes, DACs/ADCs, references, regulators).
• Strong understanding of physical-layer design, signal integrity, and high-speed I/O.
• Proficiency with design/simulation tools (Cadence Virtuoso, Spectre) and layout-aware design.

Responsibilities

• Analog & Mixed-Signal Design: Architect and design high-speed analog/mixed-signal circuits (PLLs, LDOs, references, SerDes front-ends, ADCs/DACs, clocks).
• Silicon Execution & Validation: Lead silicon bring-up, characterization, debugging, and test planning.
• Technical Leadership: Set design methodology, review standards, and mentor engineers across teams.

Skills

Analog design

Mixed-signal

High-speed I/O

Signal integrity

Cadence tools

Layout awareness

Education

MS or PhD in Electrical Engineering

Tools

Cadence Virtuoso

Spectre

Job description

Astera Labs is redefining AI connectivity in rack-scale infrastructure. The Principal Analog Design Engineer will own the design of high-performance analog and mixed-signal circuits for SerDes, PHY, and high-speed I/O, shaping performance, power, and reliability in data centers.

You will lead from concept through silicon bring-up, mentor engineers, set technical standards, and collaborate with digital, physical design, and systems teams to deliver full-chip solutions for next-gen AI compute.