Principal SerDes Design Engineer - AI Interconnect Leader

Celero Communications, Inc.; Irvine (CA); On-site; USD 150,000 - 250,000; Full time

Job summary

Celero Communications, Inc. is seeking a Senior to Principal SerDes Design Engineer located in Irvine, CA. In this role, you will define the architecture and design high-performance SerDes for next-generation AI applications.

Ideal candidates have extensive experience in SerDes design, preferably with a Master’s degree or PhD in Electrical Engineering. The position offers a competitive annual salary range of $150,000 to $250,000 based on experience and qualifications.

Qualifications

• 10+ years of relevant experience in SerDes design.
• Proven record of taking high-speed SerDes design to production.
• Experience in lab bring-up and debugging designs.

Responsibilities

• Define architecture and specifications for SerDes.
• Design high-performance analog circuits in advanced technologies.
• Lead lab validation and debugging of SerDes IPs.

Skills

SerDes design

Analog/mixed-signal circuit design

Circuit topologies

High-speed PLLs

Power Integrity analysis

Education

Master’s degree or PhD in Electrical Engineering

Tools

MATLAB

SystemVerilog

Verilog-A

Job description

Celero Communications, Inc. is seeking a Senior to Principal SerDes Design Engineer located in Irvine, CA. In this role, you will define the architecture and design high-performance SerDes for next-generation AI applications.

Ideal candidates have extensive experience in SerDes design, preferably with a Master’s degree or PhD in Electrical Engineering. The position offers a competitive annual salary range of $150,000 to $250,000 based on experience and qualifications.