Lead RTL Design Architect - NoC & High-Speed Interconnects

Architect Labs; Palo Alto (CA); Vor Ort; USD 180.000 - 240.000; Vollzeit

Zusammenfassung

Architect Labs is seeking a senior RTL Design Engineer to own the on-chip fabric and NoC architecture for production silicon. You will drive the end-to-end RTL flow from architecture through synthesis, ensuring timing closure and high-bandwidth, low-latency interconnects across the SoC.

You will work closely with DV, SW, and ML teams to refine microarchitectural specs, implement AMBA-based fabrics, and enable FPGA prototyping for early validation of the interconnect stack.

Qualifikationen

• Degree in Electrical Engineering, Computer Engineering, or closely related field.
• 5+ years of RTL design experience; 10+ years preferred.
• Deep familiarity with ARM AMBA protocol suite: AXI4/AXI5, ACE, CHI.

Aufgaben

• Own the on-chip fabric RTL end-to-end from NoC topology to timing closure.
• Design AMBA-based interconnect fabrics including AXI/ACE/CHI crossbars and network interfaces.
• Architect NoC routers and topologies with QoS, deadlock-free design, and adaptive routing.
• Build and maintain RTL infrastructure and AI-driven design flow tooling.
• Collaborate with DV, SW, and ML teams to refine interconnect specifications and validate performance.
• Support FPGA prototyping on Xilinx platforms for early validation.

Kenntnisse

RTL design

SystemVerilog

NoC routing

Python

SoC interconnect

Ausbildung

Bachelor’s/Master’s/PhD in Electrical Engineering or Computer Engineering

Tools

Vivado

Vitis

BookSim

Garnet

Jobbeschreibung

Architect Labs is seeking a senior RTL Design Engineer to own the on-chip fabric and NoC architecture for production silicon. You will drive the end-to-end RTL flow from architecture through synthesis, ensuring timing closure and high-bandwidth, low-latency interconnects across the SoC.

You will work closely with DV, SW, and ML teams to refine microarchitectural specs, implement AMBA-based fabrics, and enable FPGA prototyping for early validation of the interconnect stack.