Senior RTL Design Engineer - Low-Power SoC & Equity

Efficient Computer; San Francisco, Pittsburgh, Austin (CA, Allegheny County, TX); On-site; USD 180,000 - 245,000; Full time

Benefits offered by this job

Equity

401(k) match

Company-paid benefits

Parental leave

Flexible work options

Job summary

Efficient Computer in San Francisco, CA is seeking a Senior Design Engineer to design, integrate, and sign off RTL for blocks across the power-efficient SoC, including on-chip interconnects and memory interfaces. You will take blocks from microarchitecture specs through synthesis-ready RTL and help tape out industry-leading ultra-low-power solutions.

This is a hands-on role joining a growing HW engineering team as we move from initial product development to market release and scaled volume

Qualifications

• 8–10 years in front-end digital design for processor/SoC.
• Contributed to at least two tapeout cycles.
• Strong SystemVerilog for synthesizable RTL.
• Experience with UPF-driven low-power design.
• Knowledge of on-chip memory interfaces.

Responsibilities

• Design, integrate, and sign off RTL blocks for the compute fabric and peripheral subsystems.
• Integrate IPs (RISC-V cores, NVM controllers, SRAM wrappers, I2S/I2C) at subsystem/SoC level.
• Maintain design docs and present reviews to architecture, DV, and physical design.
• Maintain front-end quality: lint, CDC/RDC, LEC, SDC constraints, and timing closure.
• Support silicon bring-up with RTL-level debug in lab validation.

Skills

SystemVerilog RTL

Front-end design

Low-power design

Synthesis/LEC/STA

UPF power domains

NoC/Interconnect

Bus protocols (AXI/NoC)

Waveform debugging

Tools

Lint tools

CDC/RDC analysis

Synthesis toolchain

STA/timing tools

Job description

Efficient Computer in San Francisco, CA is seeking a Senior Design Engineer to design, integrate, and sign off RTL for blocks across the power-efficient SoC, including on-chip interconnects and memory interfaces. You will take blocks from microarchitecture specs through synthesis-ready RTL and help tape out industry-leading ultra-low-power solutions.

This is a hands-on role joining a growing HW engineering team as we move from initial product development to market release and scaled volume