Senior NoC & Fabric RTL Architect

TYLsemi; United States; Hybrid; USD 180,000 - 260,000; Full time

Job summary

TylSemi, Inc. is seeking a SoC Fabric micro-architect and RTL designer for chiplet-based AI and HPC silicon development. Define on-chip fabric topologies, data-path routing, register-access networks, arbitration, QoS, and the fabric error-handling and CDC strategies.

Own top-level fabric RTL and integration netlists, coordinating with subsystem leads to align interfaces and reset sequencing. The role requires 8+ years in digital IC design, deep experience with on-chip interconnect protocols such

Qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or equivalent with 8+ years of digital IC design, with at least 4 years owning on-chip interconnect, bus fabric, or NoC architecture at block-lead or integration-lead level.
• Deep expertise in on-chip interconnect protocols such as AXI4, AXI4-Lite, AXI-Stream, CHI or equivalent; ability to write and review bus bridge RTL and understand ordering rules, response channels, and error signaling.
• Experience with NoC design or integration of commercial NoC IP in a complex SoC.
• Familiarity with AMBA CHI or ACE coherency extensions and their impact on fabric design.
• Solid understanding of CDC design, async FIFO, gray-code counters, synchronizers, and CDC verification methodology.
• Experience owning the top-level integration netlist or chip-level assembly RTL on a multi-block design.
• Strong SystemVerilog skills for arbiters, FIFOs, pipelines, address decoders, and parameterized bus infrastructure.
• Experience with static timing constraints for multi-clock designs

Responsibilities

• Define on-chip fabric topologies connecting the multiple subsystems
• Specify the data-path fabric for high-bandwidth routes including bandwidth provisioning, pipeline depth, buffering, and back-pressure
• Architect the register-access fabric with address decoding and access-protection logic
• Define arbitration and QoS policy for shared fabric resources across traffic classes
• Own the fabric error-handling architecture: detect, log, and report illegal accesses, timeouts, and protocol violations
• Own the CDC strategy for every clock-domain boundary and document timing constraints
• Own or review all fabric RTL: bus bridges, async FIFOs, arbiters, decoders, and pipeline registers
• Drive integration assembly: top-level connectivity netlist instantiating major blocks through fabric
• Coordinate with subsystem leads on interfaces, handshake semantics, and reset sequencing at fabric boundaries
• Define and own fabric performance model and identify bottlenecks across traffic modes
• Establish fabric bring-up tests: register accessibility, path connectivity, and loopback sequences before full integration
• Coordinate with physical design on floorplan implications driven by data flow and timing closure

Skills

8+ years in digital IC design

SoC interconnect architecture

SystemVerilog

NoC/IP integration

AXI4/AXI4-Lite/AXI-Stream

CDC design

Clock-domain crossing

RTL review/ownership

Education

BS/MS in Electrical Engineering, Computer Engineering, or equivalent

Tools

SystemVerilog

AMBA CHI/ACE

SystemRDL/IP-XACT

RTL simulators

Job description

TylSemi, Inc. is seeking a SoC Fabric micro-architect and RTL designer for chiplet-based AI and HPC silicon development. Define on-chip fabric topologies, data-path routing, register-access networks, arbitration, QoS, and the fabric error-handling and CDC strategies.

Own top-level fabric RTL and integration netlists, coordinating with subsystem leads to align interfaces and reset sequencing. The role requires 8+ years in digital IC design, deep experience with on-chip interconnect protocols such