Interconnect Architect - RTL & Coherence Design

AMD; Austin (TX); On-site; USD 130,000 - 180,000; Full time

Job summary

AMD is seeking an experienced RTL design engineer to join the Infinity Fabric Architecture and RTL team. You will help build the next generation coherent interconnect linking CPU, GPU, and accelerators across multiple markets. Strong Verilog/SystemVerilog and high-speed design experience are essential.

You will contribute to architectural exploration, optimization, and verification, with opportunities for cross‑site collaboration and post‑silicon debugging in a fast-paced, innovative environment.

Qualifications

• Bachelor's, Master's, or PhD in Electrical/Computer Engineering or related field.
• Proven experience designing logic blocks in CPU, GPU, NOC, or cache designs.
• Strong knowledge of Verilog and SystemVerilog; experience with high-speed designs.

Responsibilities

• Early architectural and performance exploration through microarchitectural definition.
• Optimize designs to meet power, performance, area and timing targets.
• Write readable, synthesizable Verilog RTL.
• Run unit-level tests and contribute to verification quality.
• Create assertions and improve coverage; document design clearly.
• Participate in post-silicon debugging and performance tuning.

Skills

RTL design

Verilog

SystemVerilog

CPU/GPU/NOC design experience

C/C++ scripting (Python, Perl)

Digital design verification

Multi-site collaboration

Education

Bachelor's in Electrical/Computer Engineering

Master's or PhD in a related field

Tools

Verilog

SystemVerilog

C

C++

Python

Perl

Job description

AMD is seeking an experienced RTL design engineer to join the Infinity Fabric Architecture and RTL team. You will help build the next generation coherent interconnect linking CPU, GPU, and accelerators across multiple markets. Strong Verilog/SystemVerilog and high-speed design experience are essential.

You will contribute to architectural exploration, optimization, and verification, with opportunities for cross‑site collaboration and post‑silicon debugging in a fast-paced, innovative environment.