Lead RTL Design Engineer Energy-Efficient SoC with Equity

Efficient Computer Corporation, Inc.; Austin (TX); Hybrid; USD 200,000 - 275,000; Full time

Job summary

Efficient Computer is seeking a Lead RTL Design Engineer to define microarchitecture and implement RTL across the dataflow fabric, memory subsystem, NoC interconnect, and low-power logic. You will work with architects, DV leads, and firmware teams to tape out a power-efficient SoC for edge computing and data centers.

You will mentor engineers, drive PPA tradeoffs, and contribute to silicon bring-up while collaborating with compiler teams to optimize hardware execution of graph workloads.

Qualifications

• 8+ years of RTL design experience with tape-out ownership of dataflow based design, on chip networks, memory subsystems or peripheral integration on a processor or accelerator SoC.
• Deep proficiency in SystemVerilog for RTL — synthesis-clean, lint-clean, timing-aware; able to design complex state machines, arbiters, token flow controllers, and datapath logic from scratch.
• Solid understanding of parallel execution models: dataflow, SIMD, or systolic array architectures; familiarity with token-based firing-rule evaluation and producer-consumer synchronization.
• Hands-on experience with on-chip memory design: SRAM wrappers, scratchpad/TCM, banking, and memory-mapped register interfaces.
• Experience with low-power RTL techniques: UPF-driven flows, clock gating, power domains, retention registers, and AON wakeup logic.
• Familiarity with at least one standard on-chip bus protocol (AXI, AHB, APB, TileLink, or NoC equivalent) at the RTL implementation level.
• Experience taking RTL through synthesis and timing closure; ability to read and act on SDC constraints, STA reports, and synthesis QoR summaries.
• Strong written communication skills; able to produce uArch specs and design review material independently.
• Experience with memory compiler toolchains

Responsibilities

• Own microarchitecture definition and RTL implementation across the dataflow fabric, memory subsystem, on-chip interconnect/NoC, and low-power logic.
• Define and drive on-chip networks and data movement across the fabric with performance, scalability and design constraints in collaboration with physical design.
• Define the interface to memory subsystem, data movement, ordering, and synchronization behavior for software and future expansion.
• Lead the architecture of configuration, scheduling, and execution of workloads on the fabric, including multi-kernel support and host interaction.
• Drive power architecture across the design including clocking, reset, power domains, and low-power strategies.
• Collaborate with compiler and software teams to map workloads efficiently to the architecture.
• Author and own uArch specification documents; drive design reviews with stakeholders.
• Mentor RTL engineers and support silicon bring-up with RTL-level debug guidance.

Skills

RTL design

SystemVerilog

Dataflow architectures

On-chip memory design

Low-power RTL

Bus protocols

Timing closure

Technical writing

Memory compilers

Job description

Efficient Computer is seeking a Lead RTL Design Engineer to define microarchitecture and implement RTL across the dataflow fabric, memory subsystem, NoC interconnect, and low-power logic. You will work with architects, DV leads, and firmware teams to tape out a power-efficient SoC for edge computing and data centers.

You will mentor engineers, drive PPA tradeoffs, and contribute to silicon bring-up while collaborating with compiler teams to optimize hardware execution of graph workloads.