Senior RTL Designer – Memory Subsystem & Ethernet

Architect Labs; Palo Alto (CA); On-site; USD 180,000 - 240,000; Full time

Job summary

Architect is seeking a technically seasoned RTL Design staff member to own AI-driven microarchitecture and RTL for high-performance networking subsystems. You will define block-level specs for Ethernet MAC engines, IPv4/IPv6-like datapath considerations, and tight integration into production silicon.

The role requires 5+ years in RTL design with advanced-node tapeout in NICs or switches, SystemVerilog mastery, and strong collaboration with DV, SW, and ML teams to refine timing, area, and power

Qualifications

• Degree in Electrical/Computer Engineering or closely related field.
• 5+ years in RTL design with advanced-node tapeout experience in NICs or network SoCs.
• Deep familiarity with IEEE 802.3 Ethernet standards and MAC/PCS layers.
• Hands-on experience with Ethernet MAC blocks and Tx/Rx pipelines.
• Strong SystemVerilog, synthesizable RTL and modular design practices.
• Experience with synthesis, timing constraints, and clock domain crossings.
• Proficiency in Python for design automation and test generation.

Responsibilities

• Own the network datapath RTL end-to-end from MAC engine to data path.
• Design and implement Ethernet MAC engines across multiple speeds (10G–400G+).
• Architect and optimize packet processing datapaths and DMA interfaces.
• Collaborate with the principal architect to refine microarchitectural specs and trade-offs.
• Define and maintain interface specs (MII/GMII/XGMII/CGMII, AXI-Stream, AXI).
• Build and maintain RTL infrastructure and AI-driven design flows.
• Support DV with protocol-aware models and SVA assertions.
• Collaborate with SW/ML to improve AI-driven design flows.
• Support FPGA prototyping for early functional validation.

Skills

RTL Design

SystemVerilog

Ethernet MAC

Packet Datapath

Python

Synthesis

SoC Integration

Education

Bachelor’s, Master’s, or PhD in Electrical/Computer Engineering or related field

Tools

Xilinx Vivado

Job description

Architect is seeking a technically seasoned RTL Design staff member to own AI-driven microarchitecture and RTL for high-performance networking subsystems. You will define block-level specs for Ethernet MAC engines, IPv4/IPv6-like datapath considerations, and tight integration into production silicon.

The role requires 5+ years in RTL design with advanced-node tapeout in NICs or switches, SystemVerilog mastery, and strong collaboration with DV, SW, and ML teams to refine timing, area, and power