Lead, Physical Design for High-Performance ASIC TPU

Google LLC; Sunnyvale (CA); On-site; USD 167,000 - 278,000; Full time

Job summary

Google LLC is seeking a Physical Design Technical Lead for ASIC/TPU in Sunnyvale, CA. You will lead physical design execution from RTL to GDSII, drive timing closures, and coordinate with RTL, DFT, methodology, and packaging teams to optimize power, performance, and area.

Responsibilities include managing schedules, mitigating risks, and guiding cross-functional collaboration with internal teams and external vendors. Strong leadership and communication are essential.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field or equivalent practical experience.
• 10 years of experience in physical design, leading full-chip or sub-chip implementation and timing closure.
• Experience with RTL2GDSII and sign-off processes.

Responsibilities

• Lead physical design implementation and strategy for high-performance silicon across project phases.
• Manage RTL to GDSII flow, including timing, power integrity, and electrical performance sign-offs.
• Partner with RTL, DFT, methodology, and packaging teams for optimal PPA results.
• Collaborate with external EDA and IP vendors to improve flows and methodologies.
• Drive execution schedules, resource planning, and risk mitigation across the area of ownership.

Skills

Leadership

Cross-functional collaboration

Education

Bachelor's degree in EE/CE/CS

Tools

Python

Tcl

Perl

Cadence Innovus

Synopsys DP

Mentor Calibre

Job description

Google LLC is seeking a Physical Design Technical Lead for ASIC/TPU in Sunnyvale, CA. You will lead physical design execution from RTL to GDSII, drive timing closures, and coordinate with RTL, DFT, methodology, and packaging teams to optimize power, performance, and area.

Responsibilities include managing schedules, mitigating risks, and guiding cross-functional collaboration with internal teams and external vendors. Strong leadership and communication are essential.