Physical Design Technical Lead, ASIC, TPU

Google LLC; Sunnyvale (CA); On-site; USD 167,000 - 278,000; Full time

Job summary

Google LLC is seeking a Physical Design Technical Lead for ASIC/TPU in Sunnyvale, CA. You will lead physical design execution from RTL to GDSII, drive timing closures, and coordinate with RTL, DFT, methodology, and packaging teams to optimize power, performance, and area.

Responsibilities include managing schedules, mitigating risks, and guiding cross-functional collaboration with internal teams and external vendors. Strong leadership and communication are essential.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field or equivalent practical experience.
• 10 years of experience in physical design, leading full-chip or sub-chip implementation and timing closure.
• Experience with RTL2GDSII and sign-off processes.

Responsibilities

• Lead physical design implementation and strategy for high-performance silicon across project phases.
• Manage RTL to GDSII flow, including timing, power integrity, and electrical performance sign-offs.
• Partner with RTL, DFT, methodology, and packaging teams for optimal PPA results.
• Collaborate with external EDA and IP vendors to improve flows and methodologies.
• Drive execution schedules, resource planning, and risk mitigation across the area of ownership.

Skills

Leadership

Cross-functional collaboration

Education

Bachelor's degree in EE/CE/CS

Tools

Python

Tcl

Perl

Cadence Innovus

Synopsys DP

Mentor Calibre

Job description

Physical Design Technical Lead, ASIC, TPU

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• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 10 years of experience in physical design, including leading full-chip or sub-chip implementation such as RTL2GDSII and overseeing key stages like floorplanning, place and route, and timing closure for high-speed ASICs across various process nodes.
• Experience in Python, Tcl, or Perl scripting.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with Cadence Innovus, Synopsys DP, Mentor Calibre, and StarRC, plus understanding of foundry technology files, rule decks, physical sign-off, and 2.5D/3D packaging.
• Technical leadership experience managing execution schedules, mitigating risks, and driving cross-functional collaboration with internal teams and external vendors.
• Understanding of performance, power, and area trade-offs, alongside knowledge of DFT including Scan, MBIST, and LBIST.
• Ability to navigate ambiguity, scale leadership across the physical design hierarchy, and excellent communication skills to articulate complex technical challenges to stakeholders.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Google’s Tensor Processing Units (TPUs) are incredibly complex, pushing the boundaries of physical design, power, and performance. In this role, you will provide technical leadership for the physical design of our next-generation AI silicon. Because of the sheer scale of our chips, our physical design leadership is highly dynamic; you will be expected to drive end-to-end execution with a scope that scales from owning highly complex, critical macro-subsystems up to overarching project-wide top-level implementation, depending on project needs.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $192000 - $278000 (USD) + 20% bonus target + equity + benefits

• Lead the physical design implementation and strategy for high-performance silicon, with leadership scope ranging from critical, high-complexity subchips to overarching top-level execution based on project phases and team needs.
• Manage the full design cycle from RTL to GDSII, including critical sign-off closures for timing, electrical performance, and power integrity.
• Partner with internal teams (RTL, DFT, methodology, packaging) to achieve optimal power, performance, and area (PPA) results, including conducting feasibility studies for new microarchitectures and optimizing RTL runs.
• Collaborate with external EDA and IP vendors to improve flows and methodologies, while contributing to internal processes to ensure efficient and predictable execution.
• Drive execution schedules, resource planning, and risk mitigation for your area of ownership, scaling your leadership to support overall project-wide milestones.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.