STA Lead for AI ASIC Timing & Convergence

Google Inc.; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google Sunnyvale, CA, USA seeks a Physical Design Lead focused on Static Timing Analysis to drive complex ASIC timing convergences with experienced leadership. You will shape STA methodology, margins, and automation while collaborating with architecture, RTL, and DFT teams to ensure timing closure for high-performance TPU/AI compute blocks.

You will guide constraint development, sign-off processes, and cross-functional debugging, delivering robust silicon on time while interacting with EDA

Qualifications

• Bachelor’s degree or equivalent practical experience in a relevant field.
• 10+ years in static timing analysis with 5+ years in technical leadership.
• Experience authoring/reviewing timing constraints (SDC).
• Experience with Tcl for timing analysis, closure, extraction, noise, or crosstalk.
• Experience with industry EDA tools (PrimeTime/Tempus/Timevision/STAR-RC).
• Experience analyzing cross-chip clock distribution networks.

Responsibilities

• Lead timing constraint creation, validation, and ECO for complex ASICs.
• Drive STA methodology development and timing sign-off.
• Develop flows around standard STA and parasitic extraction tools.
• Collaborate with RTL, DFT, and architecture teams for cross-functional requirements.
• Triage tool issues with EDA vendors and deliver timely solutions.

Skills

Static timing analysis

Leadership

Constraint development

Tcl scripting

EDA tools

Clock networks analysis

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science or related field

Master's or PhD in Electrical/Computer Engineering or Computer Science (preferred)

Tools

PrimeTime

Tempus

Timevision

STAR-RC

SDC (Design Constraints)

Job description

Google Sunnyvale, CA, USA seeks a Physical Design Lead focused on Static Timing Analysis to drive complex ASIC timing convergences with experienced leadership. You will shape STA methodology, margins, and automation while collaborating with architecture, RTL, and DFT teams to ensure timing closure for high-performance TPU/AI compute blocks.

You will guide constraint development, sign-off processes, and cross-functional debugging, delivering robust silicon on time while interacting with EDA