Senior Low-Power Physical Validation Engineer – TPU ASICs

Google; Sunnyvale (CA); On-site; USD 163,000 - 237,000; Full time

Benefits offered by this job

15% bonus target

Equity opportunities

Comprehensive benefits

Job summary

Google is seeking a Physical Low Power Validation Engineer in Sunnyvale, California, to shape the future of AI/ML hardware acceleration. In this role, you'll drive cutting-edge TPU technology responsible for Google's most demanding applications.

Ideal candidates will have extensive experience in ASIC design and validation methodologies. You will lead technical engagements to ensure the integrity of multi-voltage ASIC implementations while bridging front-end architectures and physical execution.

Qualifications

• Bachelor's degree or equivalent experience with 8 years in ASIC design.
• Experience with low-power verification methodologies.
• Familiar with timing-driven Place and Route algorithms.

Responsibilities

• Design and deploy low power verification methodologies.
• Validate complex multi-voltage design collateral.
• Drive the resolution of Physical Design anomalies.

Skills

Post-layout physical netlist validation

Low-power signoff

Static low-power rule checking tools

Debugging signal corruption

Experience with IEEE 1801 UPF

Scripting languages (Tcl, Python)

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field

Master's degree or PhD in related fields

Tools

Synopsys VCLP

Innovus

Fusion

Job description

Google is seeking a Physical Low Power Validation Engineer in Sunnyvale, California, to shape the future of AI/ML hardware acceleration. In this role, you'll drive cutting-edge TPU technology responsible for Google's most demanding applications.

Ideal candidates will have extensive experience in ASIC design and validation methodologies. You will lead technical engagements to ensure the integrity of multi-voltage ASIC implementations while bridging front-end architectures and physical execution.