ASIC Physical Design Lead — TPU Architect, PNR & Timing

Google LLC; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google LLC in Sunnyvale, CA is seeking an experienced hardware design senior to shape the future of AI/ML hardware acceleration. You’ll drive TPU technology, developing custom silicon that powers Google's demanding AI/ML workloads, with a focus on verification of complex digital designs and integration within AI/ML systems.

You will empower Google and customers with breakthrough silicon leadership at scale, shaping hyperscale computing across TPUs and related platforms, with a strong emphasis on

Qualifications

• Bachelor's degree in EE/CE/CS or equivalent; 10 years in physical design.
• Experience hardening dense compute units into high-frequency macros.
• Knowledge of sub-7nm FinFET and GAA architectures and datapath density.

Responsibilities

• Own critical datapath and MAC blocks from RTL to GDSII, including PNR.
• Perform feasibility studies for PPA tradeoffs and timing closure.
• Develop physical design methodologies for dense blocks and metal-fill impact.
• Lead a small team, provide technical guidance, and ensure on-schedule delivery.
• Collaborate on TPU architecture integration within AI/ML systems.

Skills

Physical design

Datapath design

RTL to GDSII

Synthesis & PnR

Power/Performance optimization

Education

Bachelor's degree in EE/CE/CS or equivalent

Master's degree or PhD preferred

Tools

Synthesis tools (e.g., Fusion Compiler)

Place & Route tools (Innovus/Genus)

Timing analysis (PrimeTime)

DRC/LVS tools (Calibre)

Job description

Google LLC in Sunnyvale, CA is seeking an experienced hardware design senior to shape the future of AI/ML hardware acceleration. You’ll drive TPU technology, developing custom silicon that powers Google's demanding AI/ML workloads, with a focus on verification of complex digital designs and integration within AI/ML systems.

You will empower Google and customers with breakthrough silicon leadership at scale, shaping hyperscale computing across TPUs and related platforms, with a strong emphasis on