TPU Compute ASIC Verification Lead

Google; Sunnyvale (CA); On-site; USD 192,000 - 278,000; Full time

Job summary

Google is seeking an ASIC Design Verification Manager for TPU workloads in Sunnyvale, CA. You will lead a team responsible for the functional verification of major TPU compute components, defining verification strategies, and building scalable test environments.

You will mentor engineers, drive verification quality standards, and collaborate with architecture, design, and power teams to meet performance and efficiency goals in a fast-paced AI/ML hardware context.

Qualifications

• Bachelor's degree or equivalent practical experience in a related field.
• 10 years of experience with verification, SystemVerilog, and UVM.
• 3 years of people management experience.

Responsibilities

• Lead the functional verification team for TPU compute components.
• Define and drive verification strategies for complex compute subsystems.
• Architect scalable, reusable verification environments and flows.
• Provide technical leadership and mentorship to junior engineers; drive reviews and standards.
• Partner with architects and design leads to influence micro-architectural decisions.

Skills

SystemVerilog/UVM

Verification

People management

Cross-functional collaboration

Architectural verification

Test plan development

AI/ML accelerator experience

Verification infrastructure

Education

Bachelor's degree in EE/CE/CS or equivalent

Master's or PhD in EE/CE/CS (computer architecture)

Job description

Google is seeking an ASIC Design Verification Manager for TPU workloads in Sunnyvale, CA. You will lead a team responsible for the functional verification of major TPU compute components, defining verification strategies, and building scalable test environments.

You will mentor engineers, drive verification quality standards, and collaborate with architecture, design, and power teams to meet performance and efficiency goals in a fast-paced AI/ML hardware context.