Senior VLSI Design Engineer – Timing & ASIC Expert

Broadcom; Fort Collins (CO); On-site; USD 129,000 - 207,000; Full time

Benefits offered by this job

Medical, dental, vision

401(K) with company match

Employee Stock Purchase Program (ESPP)

Paid holidays and time off

Job summary

Broadcom in Fort Collins, CO is seeking a senior engineer with deep VLSI/ASIC design and timing analysis expertise to tackle complex development and support challenges across global teams.

You will apply static timing analysis tools (PrimeTime, Cadence Tempus), model RC networks, and develop timing constraints while collaborating with engineers across time zones. Strong TCL and scripting skills are required.

Qualifications

• Strong understanding of VLSI and ASIC physical design.
• Experience using a static timing analysis tool such as PrimeTime or Tempus.
• Understanding of RC networks and timing propagation; ability to create timing diagrams.
• Proficiency in Python/Ruby, TCL, BASH.
• Excellent collaboration across geographies and multiple teams.

Responsibilities

• Works on significant development and support issues requiring deep analysis.
• Exercises independent judgment in methods and evaluation criteria.
• Creates formal networks involving coordination among groups and across time zones.
• Organizes and presents data clearly and manages multiple tasks.

Skills

VLSI/ASIC design

Timing analysis

STA concepts

Signal integrity

Communication across geographies

Scripting (TCL)

Education

B.S. in Electrical/Computer Engineering

Tools

Synopsys PrimeTime

Cadence Tempus

SPICE analysis

Job description

Broadcom in Fort Collins, CO is seeking a senior engineer with deep VLSI/ASIC design and timing analysis expertise to tackle complex development and support challenges across global teams.

You will apply static timing analysis tools (PrimeTime, Cadence Tempus), model RC networks, and develop timing constraints while collaborating with engineers across time zones. Strong TCL and scripting skills are required.