Lead IC Design Engineer: STA, Synthesis & Timing Closure

Broadcom, Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

401(k) matching

Employee Stock Purchase Program (ESPP)

Paid holidays

Paid sick leave and vacation

Job summary

Broadcom, Inc. in San Jose, CA seeks a lead STA/Synthesis engineer to drive timing closure for complex IP and ASIC blocks in advanced nodes.

You will develop timing constraints, run static timing analysis with PrimeTime/Tempus, perform synthesis and timing audits, and automate analysis with Tcl or Perl; provide clock tree guidance.

Requires 12+ years in high‑complexity silicon, RTL/P&R experience, and strong collaboration skills.

Qualifications

• Experience with high-complexity silicon in advanced technology nodes.
• Timing constraint development for hierarchical designs.
• Knowledge of clock tree planning and SoC implementation.
• Experience with timing ECO creation and final signoff.
• Proficiency with STA tools (PrimeTime/TCM/Tempus) and scripting.
• Proficiency with synthesis and audit tools (DC-T/Genus/Fishtail/VCLP/Formality).
• Strong RTL and place-and-route understanding.
• Excellent problem-solving and teamwork skills.

Responsibilities

• Develop and validate timing constraints for intricate SoCs.
• Perform STA using PrimeTime/Tempus and run synthesis with audits.
• Define timing signoff methodologies across corners and derates.
• Conduct pre-route timing checks and QoR analysis.
• Automate timing analysis with Tcl/Perl scripting.
• Guide clock tree synthesis and energy-efficient optimizations.
• Ensure compliance with timing signoff checklists and criteria.
• Generate timing ECOs and drive timing closure for IP/ASIC blocks.

Skills

STA/Timing analysis

Scripting (Tcl, Perl)

Clock tree planning

Timing signoff

Problem-solving

Communication

Teamwork

Independent work

Education

Bachelor's degree in a related field

MS/PhD considered

Tools

PrimeTime

Tempus

TCM

Tempus

DC-T

Genus

Fishtail

VCLP

Formality

Job description

Broadcom, Inc. in San Jose, CA seeks a lead STA/Synthesis engineer to drive timing closure for complex IP and ASIC blocks in advanced nodes.

You will develop timing constraints, run static timing analysis with PrimeTime/Tempus, perform synthesis and timing audits, and automate analysis with Tcl or Perl; provide clock tree guidance.

Requires 12+ years in high‑complexity silicon, RTL/P&R experience, and strong collaboration skills.