Senior STA Engineer - AI-Driven Timing for 3nm ASICs

Broadcom, Inc.; San Jose (CA); On-site; USD 144,000 - 230,000; Full time

Benefits offered by this job

Medical, dental and vision plans

401(K) with company matching

ESPP

Employee Assistance Program (EAP)

Paid holidays

Paid sick leave and vacation

Job summary

Broadcom, Inc. in San Jose, CA is seeking a Principal Physical Design Engineer, STA for the ASIC Products Division. This highly visible role focuses on full‑chip timing sign‑off across PVT corners using AI‑driven automation to accelerate timing closure and improve efficiency.

You will collaborate with RTL, Physical Design and DFT teams to optimize PPA, maintain SDCs, and push MMMC, OCV and IR‑drop strategies across 3nm/2nm processes. Strong scripting is essential.

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering with 12+ years of hands‑on ASIC STA and timing closure experience.
• Expert proficiency in sign‑off tools (PrimeTime/Tempus) and advanced MMMC/OCV management.
• Strong scripting skills (Tcl, Python, Perl, Shell) with a track record of using AI plugins and data‑mining scripts for runtime reduction and reporting.
• Soft skills: problem solving and strong communication.

Responsibilities

• Full‑Chip Timing Sign‑off & Constraints: Own final timing closure across PVT corners, authoring and maintaining SDC for functional and test modes.
• AI & Infrastructure Optimization: Deploy AI/ML automation within STA flows to minimize runtime and maximize server/infrastructure efficiency, with ML‑based corner reduction.
• Triaging & Marginalities: Use automated workflows and data‑mining to triage violations, isolate root causes, and eliminate timing and design marginalities across clock networks and multi‑die boundaries.
• Methodology, ECOs & Collaboration: Drive timing ECOs and collaborate with RTL, Physical Design, and DFT teams to optimize PPA.

Skills

PrimeTime/Tempus

Scripting (Tcl, Python, Perl, Shell)

AI/ML automation in STA

Education

Bachelor of Electrical/Computer Engineering

Tools

OCV concepts

IR‑drop concepts

Automation tooling

Job description

Broadcom, Inc. in San Jose, CA is seeking a Principal Physical Design Engineer, STA for the ASIC Products Division. This highly visible role focuses on full‑chip timing sign‑off across PVT corners using AI‑driven automation to accelerate timing closure and improve efficiency.

You will collaborate with RTL, Physical Design and DFT teams to optimize PPA, maintain SDCs, and push MMMC, OCV and IR‑drop strategies across 3nm/2nm processes. Strong scripting is essential.