Remote Senior Physical Design Engineer: FinFET & 12LP

Encore Semi, Inc.; Raleigh (NC); Remote; USD 135.000 - 165.000; Vollzeit

Benefits dieser Stelle

15 days PTO per calendar year

10 paid Holidays per calendar year

Comprehensive Medical Benefits

Dental & Vision 50% premiums

Voluntary Benefits: Life Insurance, FS

401k - Traditional & Roth

Life/AD&D and Long-Term Disability

Tuition reimbursement

Zusammenfassung

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation of high-performance SoCs, tackling FinFET design challenges and driving PPA boundaries at GF 12LP.

You will own end-to-end physical design from synthesis through GDSII signoff using Synopsys Fusion Design Platform, with CTS, SD constraints, timing signoff, and reliability analyses. Must have 5+ years ASIC physical design, Fusion Compiler and PrimeTime proficiency, scripting in Tcl/Python/Perl, and

Qualifikationen

• 5+ years of ASIC physical design experience with proven tape-outs on advanced FinFET nodes (≤14nm/12nm).
• Deep hands-on proficiency with Synopsys Fusion Compiler (or ICC II) and PrimeTime.
• Strong grounding in synthesis, CTS, complex SDC constraints, and signoff methodologies.
• Solid scripting skills in Tcl, Python, or Perl.
• BS or MS in Electrical Engineering, Computer Engineering, or a related field.

Aufgaben

• End-to-End Implementation: Drive block- and top-level physical design from synthesis through GDSII signoff using the Synopsys Fusion Design Platform.
• Core P&R & Optimization: Execute floorplanning, power grid design, placement, Clock Tree Synthesis (CTS), and detail routing optimized for GF 12LP standard cell architectures.
• Timing & Signoff: Lead Static Timing Analysis (STA), parasitic extraction, and multi-corner/multi-mode closure using PrimeTime and StarRC.
• Physical Verification & Reliability: Resolve advanced FinFET physical challenges, including double patterning, DRC/LVS (ICV), and EM/IR-drop analysis (RedHawk).
• Automation: Develop Tcl and Python scripts to streamline flows, improve runtimes, and track PPA metrics.

Kenntnisse

ASIC physical design

Synopsys Fusion Compiler

PrimeTime

Scripting Tcl/Python/Perl

Ausbildung

BS or MS in Electrical/Computer Engineering

Tools

Synopsys Fusion Compiler (or ICC II)

PrimeTime

Jobbeschreibung

Encore Semi, Inc. is seeking a Senior Physical Design Engineer to lead RTL-to-GDSII implementation of high-performance SoCs, tackling FinFET design challenges and driving PPA boundaries at GF 12LP.

You will own end-to-end physical design from synthesis through GDSII signoff using Synopsys Fusion Design Platform, with CTS, SD constraints, timing signoff, and reliability analyses. Must have 5+ years ASIC physical design, Fusion Compiler and PrimeTime proficiency, scripting in Tcl/Python/Perl, and