Lead DFT Architect, Memory & Tapeout

Kepler Computing; San Jose (CA); On-site; USD 250,000 - 310,000; Full time

Job summary

Kepler Computing is seeking a highly experienced DFT Lead to own Design for Test (DFT) for memory products. You will architect, implement and drive to tapeout a complete DFT solution, balancing test coverage, time, area and power.

You will drive programmable memory BIST engines, MBIST and JTAG/boundary scan strategies, and collaborate with RTL, physical design and post-silicon teams to enable DFT-aware decisions early.

Qualifications

• 15+ years of hands-on DFT architecture and implementation experience on complex ASIC/SoC designs, with multiple silicon tapeouts.
• Deep ATPG expertise (stuck‑at, transition, path delay, cell‑aware) using industry‑standard DFT tools.
• Strong MBIST architecture and implementation experience on large designs.
• Hands‑on experience designing or modifying programmable BIST engines for memory testing, including repair flow and diagnostics.
• Strong knowledge of JTAG TAP controller design and boundary scan (BSR, BSDL, compliance).
• Solid understanding of hierarchical DFT architecture, scan chain partitioning and scan compression.
• Understanding of DFT‑aware RTL practices and how DFT interacts with physical design.
• Experience with ATE interfaces and production test program development.
• Strong scripting skills (Python, Tcl, Perl).
• Excellent communication skills with a proven ability to own complex DFT solutions end to end in a fast‑paced environment.

Responsibilities

• Own DFT architecture and implementation end to end, from definition through RTL, netlist, verification and tapeout.
• Drive the design of programmable memory BIST engines, including test algorithms, address sequencing, repair flow and fail analysis tailored to the memory architecture.
• Design repair and redundancy management (hard and soft repair, repair data storage) and fail logging and diagnostics infrastructure.
• Define DFT strategy: full-scan ATPG, embedded compression, MBIST, JTAG, boundary scan and hierarchical test integration.
• Drive test coverage closure: fault models, coverage targets and ATPG pattern optimization.
• Work with architecture, RTL, physical design, packaging and post-silicon validation teams to build DFT-aware decisions early.
• Set DFT best practices, sign-off infrastructure and documentation standards.

Skills

DFT architecture

ATPG expertise

MBIST architecture

JTAG boundary scan

Programmable BIST engines

Scripting (Python, Tcl, Perl)

Communication skills

Education

B.Tech/M.Tech/MS in EE/CE/related field

Tools

Industry-standard DFT tools

Job description

Kepler Computing is seeking a highly experienced DFT Lead to own Design for Test (DFT) for memory products. You will architect, implement and drive to tapeout a complete DFT solution, balancing test coverage, time, area and power.

You will drive programmable memory BIST engines, MBIST and JTAG/boundary scan strategies, and collaborate with RTL, physical design and post-silicon teams to enable DFT-aware decisions early.