Senior SoC DFT Architect for HBM Systems

Micron Technology, Inc.; Folsom (CA); Sur place; USD 146 000 - 247 000; Plein temps

Résumé du poste

Micron Technology, Inc. in Folsom, CA is seeking a senior SoC design for test (DFT) engineer to own DFT architectures for high-bandwidth memory systems.

You will drive DFT across RTL-to-GDS flows, implement MBIST/LBIST and boundary scan, and collaborate with RTL, STA, and physical design teams to ensure manufacturability and silicon bring-up. The role requires seven+ years in SoC DFT/DFT implementation, strong scripting skills, and experience with leading EDA tools (Siemens, Synopsys, Cadence).

Qualifications

• Strong hands-on experience with SoC develop for test (DFT) architecture and implementation.
• Experience across RTL-to-GDS flows and collaboration with synthesis, STA, and physical design teams.
• Proficiency using industry-standard EDA tools for DFT and implementation.
• Bachelor's degree in Electrical/Computer Engineering or related field.
• Seven or more years of relevant experience in SoC design, DFT, or implementation.

Responsabilités

• Own SoC-level DFT structures and their implementation (scan, MBIST/LBIST, boundary scan, JTAG).
• Define and drive DFT architecture early in the design cycle across multiple teams.
• Implement and integrate DFT logic at block, subsystem, and full-chip levels.
• Complete and sign off DFT flows including ATPG readiness and coverage closure.
• Collaborate with physical design teams to optimize DFT for placement and timing closure.
• Work with verification, test, and manufacturing teams to ensure pre/post-silicon readiness.
• Mentor engineers and drive innovation for future HBM generations.

Connaissances

SoC DFT architecture

Scan insertion

MBIST/LBIST

Boundary scan (JTAG)

ATPG

RTL-to-GDS flows

EDA tools (Siemens, Synopsys, Cadence)

Scripting (Python/Tcl/Perl)

HBM memory familiarity

Formation

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

Outils

Siemens EDA

Synopsys EDA

Cadence EDA

Description du poste

Micron Technology, Inc. in Folsom, CA is seeking a senior SoC design for test (DFT) engineer to own DFT architectures for high-bandwidth memory systems.

You will drive DFT across RTL-to-GDS flows, implement MBIST/LBIST and boundary scan, and collaborate with RTL, STA, and physical design teams to ensure manufacturability and silicon bring-up. The role requires seven+ years in SoC DFT/DFT implementation, strong scripting skills, and experience with leading EDA tools (Siemens, Synopsys, Cadence).