Lead DFT Architect for LEO Satellite SoCs

Amazon Kuiper Manufacturing Enterprises LLC; Lemon Grove (CA); On-site; USD 185,000 - 250,000; Full time

Job summary

Amazon Kuiper Manufacturing Enterprises LLC is seeking a seasoned DFT engineer to define and implement the digital chip SOCs for LEO communications. You will work with ASIC and RFIC teams to achieve high fault coverage and robust DFT flows across sub-micron nodes.

You will architect DFT solutions, develop automated scripts for DFT insertion and validation, and collaborate across sites to meet timing, power, and test objectives, including MBIST and JTAG controls.

Qualifications

• Bachelor's degree in Electrical/Communications Engineering or related field.
• 5+ years of experience in advanced DFT techniques for deep sub-micron nodes.
• Experience implementing DFT methodology and developing automated scripts for DFT Insertion and Validation.

Responsibilities

• Architect and define DFT solutions for LEO chip families.
• Improve IPs and DFT methodologies with AI flow.
• Collaborate with ASIC design teams to integrate DFT like MBIST and JTAG controllers.
• Work with RFIC teams to ensure maximum fault coverage on custom RF blocks.
• Ensure blocks meet DFT, timing and power targets with the implementation team.
• Translate ATE patterns to tester format with Test engineering.
• Support joint bring-up of digital portions of the LEO chips.

Skills

Electrical engineering

DFT techniques

Automation scripts

AI/ML flow

IC design collaboration

Education

Bachelor's degree in Electrical/Communications Engineering

Master's or Ph.D in Electrical/Communications Engineering

Tools

MBIST

JTAG controllers

Automated testing tools

Job description

Amazon Kuiper Manufacturing Enterprises LLC is seeking a seasoned DFT engineer to define and implement the digital chip SOCs for LEO communications. You will work with ASIC and RFIC teams to achieve high fault coverage and robust DFT flows across sub-micron nodes.

You will architect DFT solutions, develop automated scripts for DFT insertion and validation, and collaborate across sites to meet timing, power, and test objectives, including MBIST and JTAG controls.