Lead DFT & Production Silicon Architect

Fortell; San Jose (CA); On-site; USD 160,000 - 300,000; Full time

Benefits offered by this job

Stock options

Generous benefits package

Occasional in-person collaboration in/

Job summary

Fortell is seeking an experienced DFT Engineer to lead full-chip test architecture, collaborating across STA, physical design, memory, and test teams to deliver production-ready silicon with robust test coverage.

You will develop DFT structures (full-scan, boundary scan, memory test), implement test infrastructure using Cadence Genus/Modus, and generate ATPG vectors. The role requires Bay Area residency and occasional in-person collaboration.

Qualifications

• Experience designing DFT architectures for complex designs.
• Ability to debug DFT issues, ATPG patterns, and coverage analyses.
• Proficient in TCL scripting for automation workflows.

Responsibilities

• Develop, architect, and implement DFT structures (full-scan, boundary scan, memory test).
• Design robust DFT infra including scan chains, compression, MBIST, BIST, and JTAG.
• Generate ATPG test vectors and analyze DFT coverage for thorough fault detection.
• Perform MBIST verification and debug of memory test algorithms.
• Verify test patterns via gate-level simulations to address timing-related issues.
• Collaborate with STA, physical design, power, and memory compiler teams to resolve DFT/MBIST challenges.
• Support bring-up of scan/MBIST vectors on silicon and assist production testing.

Skills

DFT

ATPG

JTAG

MBIST

Cadence Genus

Cadence Modus

TCL scripting

Tools

Cadence Genus

Cadence Modus

Job description

Fortell is seeking an experienced DFT Engineer to lead full-chip test architecture, collaborating across STA, physical design, memory, and test teams to deliver production-ready silicon with robust test coverage.

You will develop DFT structures (full-scan, boundary scan, memory test), implement test infrastructure using Cadence Genus/Modus, and generate ATPG vectors. The role requires Bay Area residency and occasional in-person collaboration.