Principal Engineer, DFT

Kepler Computing; San Jose (CA); On-site; USD 250,000 - 310,000; Full time

Job summary

Kepler Computing is seeking a highly experienced DFT Lead to own Design for Test (DFT) for memory products. You will architect, implement and drive to tapeout a complete DFT solution, balancing test coverage, time, area and power.

You will drive programmable memory BIST engines, MBIST and JTAG/boundary scan strategies, and collaborate with RTL, physical design and post-silicon teams to enable DFT-aware decisions early.

Qualifications

• 15+ years of hands-on DFT architecture and implementation experience on complex ASIC/SoC designs, with multiple silicon tapeouts.
• Deep ATPG expertise (stuck‑at, transition, path delay, cell‑aware) using industry‑standard DFT tools.
• Strong MBIST architecture and implementation experience on large designs.
• Hands‑on experience designing or modifying programmable BIST engines for memory testing, including repair flow and diagnostics.
• Strong knowledge of JTAG TAP controller design and boundary scan (BSR, BSDL, compliance).
• Solid understanding of hierarchical DFT architecture, scan chain partitioning and scan compression.
• Understanding of DFT‑aware RTL practices and how DFT interacts with physical design.
• Experience with ATE interfaces and production test program development.
• Strong scripting skills (Python, Tcl, Perl).
• Excellent communication skills with a proven ability to own complex DFT solutions end to end in a fast‑paced environment.

Responsibilities

• Own DFT architecture and implementation end to end, from definition through RTL, netlist, verification and tapeout.
• Drive the design of programmable memory BIST engines, including test algorithms, address sequencing, repair flow and fail analysis tailored to the memory architecture.
• Design repair and redundancy management (hard and soft repair, repair data storage) and fail logging and diagnostics infrastructure.
• Define DFT strategy: full-scan ATPG, embedded compression, MBIST, JTAG, boundary scan and hierarchical test integration.
• Drive test coverage closure: fault models, coverage targets and ATPG pattern optimization.
• Work with architecture, RTL, physical design, packaging and post-silicon validation teams to build DFT-aware decisions early.
• Set DFT best practices, sign-off infrastructure and documentation standards.

Skills

DFT architecture

ATPG expertise

MBIST architecture

JTAG boundary scan

Programmable BIST engines

Scripting (Python, Tcl, Perl)

Communication skills

Education

B.Tech/M.Tech/MS in EE/CE/related field

Tools

Industry-standard DFT tools

Job description

About The Role

We’re looking for a highly experienced DFT Lead to own Design for Test (DFT) for Kepler’s memory products. You’ll architect, implement and drive to tapeout a complete DFT solution. You’ll make well-reasoned trade-offs across test coverage, test time, area overhead and power throughout.

Responsibilities

• Own DFT architecture and implementation end to end, from definition through RTL, netlist, verification and tapeout.
• Drive the design of programmable memory BIST engines, including test algorithms, address sequencing, repair flow and fail analysis tailored to the memory architecture.
• Design repair and redundancy management (hard and soft repair, repair data storage) and fail logging and diagnostics infrastructure.
• Define DFT strategy: full-scan ATPG, embedded compression, MBIST, JTAG, boundary scan and hierarchical test integration.
• Drive test coverage closure: fault models, coverage targets and ATPG pattern optimization.
• Work with architecture, RTL, physical design, packaging and post-silicon validation teams to build DFT-aware decisions early.
• Set DFT best practices, sign-off infrastructure and documentation standards.

Requirements

• B.Tech/M.Tech/MS in EE, ECE, Computer Engineering or a related field.
• 15+ years of hands‑on DFT architecture and implementation experience on complex ASIC/SoC designs, with multiple silicon tapeouts.
• Deep ATPG expertise (stuck‑at, transition, path delay, cell‑aware) using industry‑standard DFT tools.
• Strong MBIST architecture and implementation experience on large designs.
• Hands‑on experience designing or modifying programmable BIST engines for memory testing, including repair flow and diagnostics.
• Strong knowledge of JTAG TAP controller design and boundary scan (BSR, BSDL, compliance).
• Solid understanding of hierarchical DFT architecture, scan chain partitioning and scan compression.
• Understanding of DFT‑aware RTL practices and how DFT interacts with physical design.
• Experience with ATE interfaces and production test program development.
• Strong scripting skills (Python, Tcl, Perl).
• Excellent communication skills with a proven ability to own complex DFT solutions end to end in a fast‑paced environment.

Nice to Have

• Experience with memory test, repair and yield learning in high‑volume manufacturing.
• Knowledge of DFT and test strategies for 3D innovations.
• Prior startup experience with lean teams and aggressive schedules.

Compensation And Benefits

Actual compensation will be determined based on factors including, but not limited to, relevant experience, skills, qualifications, education, job responsibilities and work location.

Kepler offers a comprehensive benefits package to eligible employees, including medical, dental and vision coverage, retirement benefits, time off and additional Kepler benefits as applicable. Eligibility and benefit offerings may vary based on employment status and work location.

Equal Employment Opportunity

Kepler is an Equal Opportunity Employer. We provide equal employment opportunities to all applicants and employees and do not discriminate on the basis of race, color, religion, sex, national origin, age, disability, veteran status, or any other characteristic protected under applicable federal, state, or local law.

We believe that different backgrounds, experiences, perspectives and ideas make our team stronger and help our employees, our technology and our community thrive.

Reasonable Accommodation

Kepler is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you need a reasonable accommodation to participate in the application or interview process, please contact us at 408-365-4627 or [e-mail].

Fair Chance Hiring

Kepler will consider qualified applicants with criminal histories in accordance with applicable federal, state, and local laws, including the California Fair Chance Act. Applicants are not required to disclose criminal history before a conditional offer of employment except where otherwise permitted or required by applicable law.

Federal Contractor Notice

Kepler is a federal contractor or subcontractor and is committed to its obligations regarding equal employment opportunity. Kepler does not discriminate against qualified individuals on the basis of disability or protected veteran status and takes steps to employ and advance in employment qualified individuals with disabilities and protected veterans.

Compensation Range: $250K - $310K