Lead ASIC DFT Architect – Test & Post-Silicon

itD; United States; Hybrid; USD 150,000 - 210,000; Full time

Benefits offered by this job

Medical benefits

401k plan

Paid holidays

Job summary

itD seeks a DFT Lead to drive advanced DFT solutions across the silicon lifecycle. You will implement hardware DFT features (scan, MBIST, BISR, boundary scan) and develop reusable test methodologies in close collaboration with cross-functional teams.

Ideal candidates bring 8–10+ years in ASIC DFT, hands-on ATPG and EDA tools, and proven post-silicon debug experience. This hybrid role is based in the US with options for remote work and requires Pacific Time availability.

Qualifications

• 8–10+ years of ASIC DFT engineering experience.
• Hands-on with JTAG protocols, scan architectures, MBIST, BISR, boundary scan.
• Experience with ATPG methodologies and industry-standard EDA tools (Tessent, Xcelium, Genus, Tempus/PrimeTime).
• Hands-on post-silicon debug including production release of DFT patterns.

Responsibilities

• Lead the implementation of hardware DFT features (scan, MBIST, BISR, boundary scan) and DFT simulation setup and debugging.
• Develop DFT IP and integrate testability features into full-chip RTL designs.
• Drive reusable DFT and debug methodologies for next-gen silicon across die architectures.
• Perform post-silicon debugging, root cause analysis, and production qualification to improve yield and manufacturability.
• Collaborate with physical design, validation, and hardware teams through the silicon lifecycle.
• Design, validate, and release ATPG patterns supporting test readiness and ramp.
• Develop technical solutions and lead the broader engineering team through challenging DFT issues.

Skills

DFT engineering

JTAG & scan

ATPG methods

Post-silicon debug

Cross-functional collaboration

Education

Bachelor's or Master's in EE/CE

Tools

Tessent

Xcelium

Genus

Tempus

PrimeTime

Job description

itD seeks a DFT Lead to drive advanced DFT solutions across the silicon lifecycle. You will implement hardware DFT features (scan, MBIST, BISR, boundary scan) and develop reusable test methodologies in close collaboration with cross-functional teams.

Ideal candidates bring 8–10+ years in ASIC DFT, hands-on ATPG and EDA tools, and proven post-silicon debug experience. This hybrid role is based in the US with options for remote work and requires Pacific Time availability.