Lead DFT Architect for Next-Gen ASICs

Normal Computing Corporation; Palo Alto (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Normal Computing is seeking a Design-for-Test (DFT) Engineer to own chip-level DFT architecture and implementation for next-generation ASICs, from RTL through tapeout. The role demands leadership, strong hands-on skills in scan, ATPG, MBIST, and boundary-scan, with collaboration across RTL, verification, physical design, and silicon product engineering.

You will guide external partners, establish scalable DFT flows, and ensure manufacturing test readiness, while maintaining power, performance,

Qualifications

• 7+ years of experience in DFT implementation for complex ASICs or SoCs with tapeouts.
• Hands-on expertise in scan insertion, ATPG, scan compression, fault coverage, and test patterns.
• Experience with MBIST, boundary scan/JTAG, and RTL-to-Gate level DFT integration.
• Proficiency with leading DFT tools (Tessent, TestMAX, Modus) and scripting skills.

Responsibilities

• Own chip-level DFT architecture, including scan, ATPG, MBIST, boundary scan/JTAG, and test access infrastructure.
• Drive DFT insertion and integration across RTL, synthesis, and physical design while preserving power, performance, and area.
• Own DFT verification, pattern generation, fault coverage, and DFT signoff through tapeout.
• Collaborate with Head of Silicon Product Engineering to deliver production-ready test patterns and collateral.

Skills

DFT implementation

Scan insertion

ATPG

Test patterns

RTL integration

Python scripting

Tools

Siemens Tessent

Synopsys TestMAX

Cadence Modus

Job description

Normal Computing is seeking a Design-for-Test (DFT) Engineer to own chip-level DFT architecture and implementation for next-generation ASICs, from RTL through tapeout. The role demands leadership, strong hands-on skills in scan, ATPG, MBIST, and boundary-scan, with collaboration across RTL, verification, physical design, and silicon product engineering.

You will guide external partners, establish scalable DFT flows, and ensure manufacturing test readiness, while maintaining power, performance,