Senior ASIC Cache Controller Engineer - High-Performance SoC

Apple Inc.; Santa Clara (CA); On-site; USD 184,700 - 324,800; Full time

Job summary

Apple Inc. in Santa Clara, CA, is seeking an experienced hardware design engineer to build the cache subsystem for a high-performance System on a Chip (SoC). The role involves RTL design, micro-architecture development, and performance/power/area trade-off analysis in line with architectural guidelines.

The candidate will collaborate on front-end netlist, timing closure with the physical design team, and contribute to shaping memory hierarchy to meet demanding latency and bandwidth requirements.

Qualifications

• 10+ years of full-time ASIC design experience.
• Memory system development.
• PPA (performance/power/area) analysis.
• Cache design background including an understanding of different memory organizations and tradeoffs.
• Hands on Experience with multi-processor cache coherence protocols.
• B.S. in a relevant field.

Responsibilities

• Design and develop hardware for cache subsystem in high performance system on a chip (SoC).
• Develop cache micro-architecture based on architecture guidelines and model analysis.
• Explore architecture trade-offs in system performance, area, and power consumption.
• Develop and debug register-transfer level (RTL) design of various sections in the cache subsystem.
• Work on front-end netlist and area/timing analysis of the cache subsystem.
• Work with physical design team on the timing closure of the cache subsystem.

Skills

Memory system development

PPA analysis

Cache design

Cache coherence protocols

Bachelor's degree in a relevant field

Education

Bachelor's degree in a relevant field

Tools

RTL design tools

Job description

Apple Inc. in Santa Clara, CA, is seeking an experienced hardware design engineer to build the cache subsystem for a high-performance System on a Chip (SoC). The role involves RTL design, micro-architecture development, and performance/power/area trade-off analysis in line with architectural guidelines.

The candidate will collaborate on front-end netlist, timing closure with the physical design team, and contribute to shaping memory hierarchy to meet demanding latency and bandwidth requirements.