Senior Cache Coherency Architect - Equity Eligible

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 152,000 - 241,500; Full time

Job summary

NVIDIA Gruppe is seeking an experienced Senior Cache Coherency Architect to be part of a world-class organization that develops scalable interconnect systems powering NVIDIA products. You will define interconnect architecture, maintain performance models, and ensure architecture aligns with project requirements.

The ideal candidate holds a Master’s degree in a related field and has 5+ years in semiconductor design, with knowledge in cache coherency protocols and proficiency in C, C++, Python, and Verilog.

Competitive salary and equity options are offered.

Qualifications

• 5+ years of experience in processor or high-performance semiconductor design.
• Deep understanding of cache coherency protocols such as AXI, ACE, CHI.
• Experience developing coherent IP models for simulation and emulation.

Responsibilities

• Define consistent interconnect architecture and cache-coherency protocols.
• Collaborate with architects to align interconnect architecture with project requirements.
• Support silicon bring-up and post-silicon debug as needed.

Skills

Cache coherency protocols

C

C++

Python

Verilog

Education

Master’s degree in electrical engineering or related field

Tools

Simulation tools

Emulation tools

Job description

NVIDIA Gruppe is seeking an experienced Senior Cache Coherency Architect to be part of a world-class organization that develops scalable interconnect systems powering NVIDIA products. You will define interconnect architecture, maintain performance models, and ensure architecture aligns with project requirements.

The ideal candidate holds a Master’s degree in a related field and has 5+ years in semiconductor design, with knowledge in cache coherency protocols and proficiency in C, C++, Python, and Verilog.

Competitive salary and equity options are offered.