Senior Cache Coherency Architect

NVIDIA Gruppe; Santa Clara (CA); On-site; USD 152,000 - 241,500; Full time

Job summary

NVIDIA Gruppe is seeking an experienced Senior Cache Coherency Architect to be part of a world-class organization that develops scalable interconnect systems powering NVIDIA products. You will define interconnect architecture, maintain performance models, and ensure architecture aligns with project requirements.

The ideal candidate holds a Master’s degree in a related field and has 5+ years in semiconductor design, with knowledge in cache coherency protocols and proficiency in C, C++, Python, and Verilog.

Competitive salary and equity options are offered.

Qualifications

• 5+ years of experience in processor or high-performance semiconductor design.
• Deep understanding of cache coherency protocols such as AXI, ACE, CHI.
• Experience developing coherent IP models for simulation and emulation.

Responsibilities

• Define consistent interconnect architecture and cache-coherency protocols.
• Collaborate with architects to align interconnect architecture with project requirements.
• Support silicon bring-up and post-silicon debug as needed.

Skills

Cache coherency protocols

C

C++

Python

Verilog

Education

Master’s degree in electrical engineering or related field

Tools

Simulation tools

Emulation tools

Job description

Job Overview

We are seeking an experienced Senior Cache Coherency Architect to join our ambitious team at NVIDIA. This opportunity allows you to be part of a world‑class organization that develops scalable, low‑latency, high‑bandwidth coherent interconnect systems. These systems power groundbreaking NVIDIA products such as Grace‑CPU‑Superchip, Grace‑Hopper‑Superchip, and Vera‑Rubin.

Responsibilities

• Define consistent interconnect architecture, cache‑coherency protocols, and high‑performance on‑chip interconnect interfaces.
• Contribute to interconnect IP block specifications, build, verification, and integration into the NoC fabric to ensure cache‑coherency compliance.
• Collaborate with architects to guarantee the interconnect architecture aligns with project power, performance, and area (PPA) requirements.
• Develop and maintain functional and performance models for the NoC fabric and IP units to assist with analysis and validation.
• Collaborate with cross‑functional design and verification teams (simulation, emulation, and formal) to ensure implementations align with architectural specifications.
• Support silicon bring‑up and post‑silicon debug as needed.

Qualifications

• Master’s degree in electrical engineering, Computer Engineering, Computer Science, or equivalent experience.
• 5+ years of experience in processor design or other high‑performance semiconductor designs.
• Deep understanding of cache coherency, with hands‑on experience in industry‑standard protocols (e.g., AXI, ACE, CHI).
• Experience authoring specifications and designing cache‑coherent interconnects.
• Strong understanding of system and memory subsystem architecture, with a focus on cache‑coherent interconnect.
• Experience developing coherent IP models (e.g., VIPs, BFMs) for simulation and emulation.
• Proficiency in C, C++, Python, and Verilog.

Compensation and Benefits

Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $152,000USD–$241,500USD for Level3, and $184,000USD–$287,500USD for Level4. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until April24,2026.

NVIDIA is committed to fostering a diverse work environment and is an equal opportunity employer. We do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.