Senior Design Engineer - High Speed Cache

Tachyum; Las Vegas (NV); On-site; USD 110,000 - 180,000; Full time

Benefits offered by this job

Competitive salary

Professional development

International environment

Bleeding‑edge technology

Collaborative work environment

Job summary

Tachyum is seeking a Physical Design Engineer to contribute to a high‑performance L2 cache unit for cutting‑edge AI processing elements. The role is based in Las Vegas or Sunnyvale, with on‑site collaboration across teams.

You will work on processor pipelines, cache coherency, and low‑power techniques using Verilog/SystemVerilog, synthesis, STA, and related tools. Candidates with 2–4 years of experience are welcome to apply.

Qualifications

• 2–4 years of experience in physical design or related areas; bright individuals considered with less.
• Experience with high speed and low power processor pipelines / ASICs / SoCs.
• Strong understanding of computer architecture and cache coherency.
• Verilog/SystemVerilog, synthesis, STA, CDC, and lint experience.

Responsibilities

• Work on high performance L2 Cache unit for AI processing elements.
• Collaborate with design teams to optimize timing, power, and area.

Skills

High speed design

Low power design

Processor pipelines

ASICs/SoCs

Multi-core

Computer architecture

Cache design

Verilog/SystemVerilog

Synthesis & STA

CDC & lint

ARM/x86

C & scripting

Job description

We are seeking a Physical Design Engineer to work on a high‑performance L2 cache unit designed to support cutting‑edge AI processing elements.

Location(s)

• Las Vegas, NV
• Sunnyvale, CA

Responsibilities

• Working on high performance L2 Cache unit serving the needs of state‑of‑the‑art AI processing elements.

Qualifications

• Requires 2 to 4 years of experience (will consider bright individuals even with lower experience) and the following skills:
• Understanding of high speed and low power processor pipeline designs / ASICs / SoCs and multi‑core designs.
• Strong understanding of computer architecture.
• Experience with cache controller designs, understanding of cache coherency protocols, cache hierarchy.
• Logic design experience with state of the art deep sub‑micron technologies specifically low power design techniques.
• Verilog / SystemVerilog / synthesis / Static Timing Analysis / CDC / lint.
• Knowledge of ARM and x86 and multicore processor designs is a plus.
• Knowledge of programming languages C, scripting (Perl / shell / python / awk) is a plus.
• Knowledge of cache design and coherency protocols.

Benefits

• Competitive salary and benefits package.
• Opportunities for professional development and advancement.
• International environment and further career progression.
• Getting in touch with bleeding‑edge technology.
• Collaborative and supportive work environment.