Lead ASIC Verification Engineer, High-Speed DSP & AI

Google

Sunnyvale (CA)

Presencial

USD 240 000 - 333 000

Tempo integral

Há 10 dias

Uma candidatura completa num minuto

Currículo e carta de apresentação personalizados, prontos a enviar.

Ultrapassa os filtros ATS

Vantagens oferecidas por esta oferta de emprego

Equity
Bonus target
Benefits

Resumo da oferta

Google is seeking an ASIC Design Verification Technical Lead to shape the future of TPU verification. You will define verification strategies for DSP pipelines and drive emulation and post-silicon correlation across our AI hardware accelerators.

You’ll collaborate with DSP designers and algorithms teams to ensure RTL matches pre-silicon models, and contribute to Google's hyperscale AI platforms powering products used worldwide.

Qualificações

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 12 years of experience in design verification.
  • Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.

Responsabilidades

  • Design, build, and scale constrained-random verification environments for DSP blocks.
  • Build co-simulation frameworks comparing RTL against high-level models.
  • Define functional coverage plans with covergroups and SystemVerilog Assertions.
  • Author dynamic stimulus sequences and virtual sequencers for real-world channel impairments.
  • Lead debugging of RTL and environment with algorithm and DSP teams to resolve discrepancies.

Conhecimentos

High-speed PHY verification
High-speed interface subsystems
Mixed-signal verification
SystemVerilog

Formação académica

Bachelor's degree in Electrical or Computer Engineering or related field

Ferramentas

UVM
SystemVerilog

Descrição da oferta de emprego

Google is seeking an ASIC Design Verification Technical Lead to shape the future of TPU verification. You will define verification strategies for DSP pipelines and drive emulation and post-silicon correlation across our AI hardware accelerators.

You’ll collaborate with DSP designers and algorithms teams to ensure RTL matches pre-silicon models, and contribute to Google's hyperscale AI platforms powering products used worldwide.

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