ASIC Design Verification Technical Lead, High-Speed DSP

Google LLC; Sunnyvale (CA); On-site; USD 240,000 - 333,000; Full time

Job summary

Google LLC is seeking an ASIC Design Verification Technical Lead for high-speed DSP to shape AI/ML hardware acceleration. You will drive verification architectures and lead constrained-random verification environments for TPU blocks, with emphasis on pre/post-silicon correlation and emulation strategies.

You will collaborate with DSP designers to align RTL with specifications, contribute to co-simulation frameworks, and push coverage decisions across architectural corner cases in large-scale AI

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.

Responsibilities

• Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.
• Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.
• Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.
• Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.
• Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.

Skills

SystemVerilog

UVM

constrained-random verification

RTL debugging

post-silicon correlation

emulation

co-simulation

covergroups

SystemVerilog Assertions

digital design verification

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field

Master's degree in Electrical Engineering, Computer Engineering, or a related technical field

PhD in Electrical Engineering, Computer Engineering, or a related technical field

Job description

ASIC Design Verification Technical Lead, High-Speed DSP

Share ASIC Design Verification Technical Lead, High-Speed DSP

In most instances, this position requires in-person interviews as part of the hiring process. Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Haifa, Israel; Tel Aviv, Israel.

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12 years of experience in design verification.
• Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience defining verification architectures, methodologies, and roadmaps for AI accelerators, High-Performance Computing or high-bandwidth networking silicon.
• Experience bridging the gap between Pre-Silicon verification (simulation and emulation) and Post-Silicon validation and correlation.
• Experience driving advanced verification methodologies.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

As an ASIC Design Verification Technical Lead, you will define how Google verifies the physical-layer Digital Signal Processing (DSP) pipelines powering our next-generation AI hardware accelerators. You will drive the shift toward Emulation and Post-Silicon Correlation, ensuring that our architectural reference models and pre-silicon simulations perfectly match the physical behavior of the high-speed silicon in our planetary-scale AI data centers.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job-related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Learn more about benefits at Google.

• Design, build, and scale constrained-random verification environments using SystemVerilog and UVM for high-speed physical-layer DSP blocks.
• Build co-simulation frameworks and predictors to compare RTL implementation output against high-level algorithmic models.
• Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed-point quantization effects, and numerical overflows.
• Author dynamic stimulus sequences and virtual sequencers to stress-test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high-frequency jitter profiles.
• Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.

Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .

Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.

Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.