DSP Verification Engineer for AI/ML Accelerators

Google Inc.; Sunnyvale (CA); On-site; USD 163,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

Google Inc. seeks an ASIC Design Verification Engineer specialized in Digital Signal Processing to advance AI/ML hardware acceleration. You will verify complex DSP blocks and drive verification strategy for high-speed PHY integration within TPU architectures.

The role emphasizes strong DV expertise, fixed-point math, and mixed-signal interfaces, with in-person interviews and location options including Sunnyvale, CA. In-person interviews are common for this role.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 8 years of experience in design verification (DV) with a focus on DSP, communication systems, or arithmetic logic blocks.
• Experience with scripting in Python, Perl, or Makefile for automation.

Responsibilities

• Verify RTL implementations against high-level architectural reference models (MATLAB, C++, or SystemC) using bit-exact and fixed-point verification methodologies.
• Verify the stability, tracking capability, and convergence of adaptive equalization loops (FFE, DFE) and timing recovery systems under varying channel impairments.
• Model and verify the functional interface between Digital DSP blocks and the Analog Front End (AFE) using RNM or SystemVerilog-AMS.
• Design, implement, and maintain scalable UVM-based simulation environments, SystemVerilog Assertions (SVA), and functional coverage metrics for DSP blocks.

Skills

DSP verification

Python scripting

SystemVerilog

Education

Bachelor's degree in Electrical/Computer Engineering or related

Master's degree or PhD (preferred)

Tools

MATLAB

C/C++

SystemVerilog-AMS

Python

Job description

Google Inc. seeks an ASIC Design Verification Engineer specialized in Digital Signal Processing to advance AI/ML hardware acceleration. You will verify complex DSP blocks and drive verification strategy for high-speed PHY integration within TPU architectures.

The role emphasizes strong DV expertise, fixed-point math, and mixed-signal interfaces, with in-person interviews and location options including Sunnyvale, CA. In-person interviews are common for this role.