ASIC Design Verification Technical Lead, High-Speed DSP

Google; Sunnyvale (CA); Sur place; USD 240 000 - 333 000; Plein temps

Avantages offerts par ce poste

Equity

Bonus target

Benefits

Résumé du poste

Google is seeking an ASIC Design Verification Technical Lead to shape the future of TPU verification. You will define verification strategies for DSP pipelines and drive emulation and post-silicon correlation across our AI hardware accelerators.

You’ll collaborate with DSP designers and algorithms teams to ensure RTL matches pre-silicon models, and contribute to Google's hyperscale AI platforms powering products used worldwide.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12 years of experience in design verification.
• Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.

Responsabilités

• Design, build, and scale constrained-random verification environments for DSP blocks.
• Build co-simulation frameworks comparing RTL against high-level models.
• Define functional coverage plans with covergroups and SystemVerilog Assertions.
• Author dynamic stimulus sequences and virtual sequencers for real-world channel impairments.
• Lead debugging of RTL and environment with algorithm and DSP teams to resolve discrepancies.

Connaissances

High-speed PHY verification

High-speed interface subsystems

Mixed-signal verification

SystemVerilog

Formation

Bachelor's degree in Electrical or Computer Engineering or related field

Outils

UVM

SystemVerilog

Description du poste

In most instances, this position requires in-person interviews as part of the hiring process.

Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Haifa, Israel; Tel Aviv, Israel.

Minimum qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical field.
• 12 years of experience in design verification.
• Experience in high-speed PHY layers, high-speed interface subsystems, or mixed-signal verification.

Preferred qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience defining verification architectures, methodologies, and roadmaps for AI accelerators, High-Performance Computing or high-bandwidth networking silicon.
• Experience bridging the gap between Pre-Silicon verification (simulation and emulation) and Post-Silicon validation and correlation.
• Experience driving advanced verification methodologies.

About the job

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems.

As an ASIC Design Verification Technical Lead, you will define how Google verifies the physical‑layer Digital Signal Processing (DSP) pipelines powering our next‑generation AI hardware accelerators. You will drive the shift toward Emulation and Post‑Silicon Correlation, ensuring that our architectural reference models and pre‑silicon simulations perfectly match the physical behavior of the high‑speed silicon in our planetary‑scale AI data centers.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting‑edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world‑leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Individual pay is determined by factors including job‑related skills, experience, and relevant education or training.

US: $240000 - $333000 (USD) + 25% bonus target + equity + benefits

Responsibilities

Learn more about benefits at Google .

• Design, build, and scale constrained‑random verification environments using SystemVerilog and UVM for high‑speed physical‑layer DSP blocks.
• Build co‑simulation frameworks and predictors to compare RTL implementation output against high‑level algorithmic models.
• Define and execute functional coverage plans, utilizing covergroups and SystemVerilog Assertions to verify architectural corner cases, fixed‑point quantization effects, and numerical overflows.
• Author dynamic stimulus sequences and virtual sequencers to stress‑test adaptive feedback loops under realistic channel impairments, including noise, ISI, and high‑frequency jitter profiles.
• Lead the debugging of RTL and environment failures, collaborating closely with algorithm and DSP designers to isolate and resolve discrepancies between the RTL implementation and the specification.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form .