ASIC Design Verification Engineer

AMD; Austin (TX); On-site; USD 100,000 - 130,000; Full time

Benefits offered by this job

Competitive benefits

Job summary

AMD is seeking an ASIC Design Verification Engineer in Austin, Texas, to develop cutting-edge verification methodologies for DDR technologies. The role involves working in a collaborative environment, developing verification architecture, and ensuring the quality of complex IP blocks.

The ideal candidate will have a BS/MS in Engineering or Computer Science, strong skills in SystemVerilog and UVM, and experience in ASIC verification. AMD offers competitive benefits and values diverse perspectives in its workforce.

Qualifications

• Experience in ASIC verification.
• Strong understanding of digital design and computer architecture.
• Ability to debug SystemVerilog RTL code using simulation tools.

Responsibilities

• Collaborate with IP architects to develop verification architecture.
• Participate in verification of complex IP blocks.
• Develop and maintain scripts and tools.

Skills

Analytical thinking

Problem-solving skills

Teamwork

Communication skills

Attention to detail

Education

BS/MS degree in Engineering or Computer Science

Tools

SystemVerilog

UVM

Verilog

C/C++

Linux

Windows

Job description

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative and inclusive of diverse perspectives.

The Role

The MSIP UMC team is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading‑edge DDR technologies powering data center and machine learning workloads. This team is part of the development for tomorrow’s client, server, embedded, graphics and semi‑custom chips. You will be involved in all aspects of IP verification starting from helping to create a verification architecture, defining test plans, verification environment development, and verification closure/sign‑off. You will take part in key technical leadership activities and collaborate with DV Architects and DV leads in shaping cutting‑edge verification environments for current and future programs.

The Person

Strong analytical thinking and problem‑solving skills, excellent attention to detail. Possesses good teamwork, communication and interpersonal skills. A self‑starter able to independently drive tasks to completion. Enjoy working in a fast‑paced, multi‑project team environment using state‑of‑the‑art tools and technology. Possesses a continuous improvement mindset.

Key Responsibilities

• Collaborate with IP architects to develop verification architecture, methodology, improvements, and development plans.
• Take on key technical leadership responsibilities to help current DV leads and DV architects.
• Participate in verification of complex IP blocks and take end‑to‑end ownership of key features for all projects.
• Work on test plans, verification environment development, regression, and coverage closure.
• Develop, modify and maintain VIPs, libraries, verification environments, testcases (random and directed) using SystemVerilog/UVM/SystemC.
• Triage and debug regressions.
• Analyze code and functional coverage.
• Deploy industry‑leading verification methodologies such as UVM and formal verification.
• Reproduce functional bugs found in post‑silicon in dynamic simulation and/or formal verification environments.
• Conduct and participate in code reviews.
• Develop and maintain scripts and tools to continuously improve engineering infrastructure, methodology and execution.

Preferred Experience

• ASIC verification experience.
• Strong understanding of digital design and computer architecture.
• Strong understanding and experience in block‑level constrained random verification.
• Proficiency in Verilog, SystemVerilog, C/C++, UVM, OOP, and working in Linux and Windows environments.
• ASIC design knowledge and ability to debug SystemVerilog RTL code using simulation tools.
• Experience in formal verification would be an asset.

Academic Credentials

• BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.

This role is not eligible for visa sponsorship.

Benefits

Benefits offered are described: AMD benefits at a glance.

AMD and its subsidiaries are equal‑opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third‑party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.