Lead ASIC Security IP Verification Manager

AMD; Austin (TX); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Benefits at AMD

Job summary

AMD is seeking a seasoned engineering leader for the ASIC Hardware and Firmware Co-Verification team in the Security IP Group. You will lead a high-performance team responsible for co-verification of embedded micro-processor subsystems and hardware accelerators in leading-edge SoCs, with emphasis on firmware-based verification and co-design opportunities.

You will mentor engineers, drive schedule commitments, collaborate with multi-functional partners, and develop verification architectures and

Qualifications

• Experience leading engineering teams in a distributed environment.
• Proven ability to manage hardware and firmware verification programs.
• Strong communication, writing, and presentation skills.

Responsibilities

• Lead a high-performance engineering team.
• Form a team and nurture talent.
• Lead team to meet schedule commitments and support customers.
• Collaborate with multi-functional leaders to drive AMD's success.
• Responsible for performance reviews and career development.
• Oversee hardware/firmware co-verification in UVM System Verilog and C-DPI testbenches.
• Develop and maintain subsystem verification architecture, testbench, and methodology.
• Develop FW/HW co-verification strategies and test plans.
• Interface with SoC integration and DV teams to drive DV efforts.

Skills

Leadership

Team management

Hardware verification

Firmware verification

UVM System Verilog

C-DPI

SoC verification

Communication skills

Education

Bachelor's or Master’s in CS/EE

Tools

UVM

SystemVerilog

C-DPI

FPGA

Job description

AMD is seeking a seasoned engineering leader for the ASIC Hardware and Firmware Co-Verification team in the Security IP Group. You will lead a high-performance team responsible for co-verification of embedded micro-processor subsystems and hardware accelerators in leading-edge SoCs, with emphasis on firmware-based verification and co-design opportunities.

You will mentor engineers, drive schedule commitments, collaborate with multi-functional partners, and develop verification architectures and