Lead ASIC Verification Engineer - SystemVerilog & UVM

WarmStart Ltd; Austin, Northern (TX, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Advanced Micro Devices, Inc. in Austin, TX is seeking a verification engineer to own verification architecture for complex IP blocks. You will collaborate with IP architects, develop test plans, and implement verification environments using UVM and SystemVerilog.

The role requires a BS/MS in engineering or CS, strong digital design knowledge, and hands-on experience with Verilog, SystemVerilog, C/C++, and Linux/Windows. Hybrid work arrangement is offered.

Qualifications

• BS/MS degree in Engineering or Computer Science.
• Strong understanding of digital design and computer architecture.
• Proficient in Verilog, System Verilog, C/C++, UVM; Linux/Windows environments.
• Knowledge of ASIC design and debugging SystemVerilog RTL code.
• Security verification experience is a plus.

Responsibilities

• Collaborate with IP architects to develop verification architecture and plans.
• Take end-to-end ownership of key features in complex IP blocks.
• Work on test plans, verification environment development, and coverage closure.
• Develop and maintain verification environments, test cases, and libraries using System Verilog/UVM/SystemC.
• Triaging and debugging regressions and analyzing code coverage.
• Deploy industry-leading verification methodologies like UVM and formal verification.
• Reproduce functional bugs found in post-silicon environments.
• Conduct code reviews and participate in team discussions.
• Develop scripts and tools to enhance engineering infrastructure and methodologies.

Skills

Analytical thinking

Attention to detail

Communication

Self-starter

Multi-project management

Education

BS/MS in Engineering or CS

Tools

Verilog

SystemVerilog

C/C++

UVM

Linux/Windows

ASIC design knowledge

Job description

Advanced Micro Devices, Inc. in Austin, TX is seeking a verification engineer to own verification architecture for complex IP blocks. You will collaborate with IP architects, develop test plans, and implement verification environments using UVM and SystemVerilog.

The role requires a BS/MS in engineering or CS, strong digital design knowledge, and hands-on experience with Verilog, SystemVerilog, C/C++, and Linux/Windows. Hybrid work arrangement is offered.