Lead ASIC Physical Design Engineer

I2Intech LLC; San Jose (CA); On-site; USD 200,000 - 260,000; Full time

Job summary

I2Intech LLC in San Jose, CA is seeking a Lead Physical Design Engineer to own the implementation flow for complex blocks and top-level integration. You will mentor a team of PD engineers and coordinate with RTL, DFT, STA and signoff teams to resolve cross-functional issues.

You will drive timing closure for high-speed designs, optimize PPA, and ensure tape-out schedules are met, with hands-on leadership across 16nm or below processes and FinFET experience.

Qualifications

• Bachelor's or Master's in Electrical Engineering required.
• 10+ years in physical design with multiple tape-outs at 16nm or below.
• Strong leadership and partner-facing communication skills.

Responsibilities

• Own floorplanning, placement, CTS, routing and timing closure for blocks and top level.
• Define and maintain the implementation flow and methodology across the team.
• Drive PPA optimisation and closure of timing, power, IR/EM and physical verification.
• Mentor and review the work of PD engineers; plan and track deliverables.
• Interface with RTL, DFT, STA and signoff teams to resolve cross-functional issues.

Skills

Physical design

Tape-out experience

Innovus

Fusion Compiler

ICC2

PrimeTime/Tempus

Calibre

Redhawk/Voltus

Tcl/Python scripting

Flow automation

Leadership

Partner-facing communication

Education

Bachelor's or Master's in Electrical Engineering

Tools

Innovus

Fusion Compiler/ICC2

PrimeTime/Tempus

Calibre

Redhawk/Voltus

Job description

Lead block and full-chip physical implementation from netlist to GDSII on advanced technology nodes.

Physical Design San Jose, CA / Austin, TX (USA)

As a Lead Physical Design Engineer you will own the implementation methodology for complex blocks and top-level integration, mentor a team of PD engineers, and be the primary technical interface with our partners' design and signoff teams. You will drive predictable timing closure on high-speed designs and ensure tape-out schedules are met.

What you'll do

• Own floorplanning, power planning, placement, CTS, routing and timing closure for blocks and top level.
• Define and maintain the implementation flow and methodology across the team.
• Drive PPA optimisation and closure of timing, power, IR/EM and physical verification (DRC/LVS/ANT).
• Mentor and review the work of PD engineers; plan and track deliverables.
• Interface with RTL, DFT, STA and signoff teams to resolve cross-functional issues.
• Lead ECO implementation and final tape-out checks.

What you bring

• Bachelor's or Master's in Electrical Engineering with 10+ years in physical design.
• Multiple tape-outs at 16nm or below; FinFET experience strongly preferred.
• Expert in Innovus or Fusion Compiler/ICC2, PrimeTime/Tempus, Calibre and Redhawk/Voltus.
• Deep understanding of CTS, low-power implementation and hierarchical design.
• Strong Tcl/Python scripting and flow automation skills.
• Demonstrated technical leadership and partner-facing communication.

Nice to have

• Experience with chiplet or multi-die implementation.
• Exposure to high-performance CPU/GPU or networking datapaths.
• Familiarity with design-for-manufacturability and yield optimisation.

Why I2Intech

You'll work on production silicon for the industry's leading semiconductor companies, in a small team where your contribution is visible and your growth is a priority. We offer competitive compensation, flexible engagement models and continuous upskilling.