Autonomous Physical Design Lead (Tapeout Ready)

Phinity Labs; San Francisco (CA); Sur place; USD 180 000 - 240 000; Plein temps

Avantages offerts par ce poste

Health insurance

Retirement plans

Unlimited PTO

Paid parental leave

Lunch and dinner provided in-office

Résumé du poste

Phinity Labs, an AI research lab in San Francisco, seeks a Physical Design Lead to drive block-to-full-chip PD flows and optimize PPA. You will define synthesis-to-layout flows, PDN, clock trees, and cell characterizations, delivering tapeout-ready designs.

You will collaborate with top researchers and hardware experts, shape strategy, and own high-impact PD initiatives across power, performance, and area trade-offs in cutting-edge accelerator chips.

Qualifications

• 5+ years leading physical design in ICs or SOCs.
• Experience delivering tapeout-ready PD designs.
• Strong knowledge of Synthesis, layout, PDN, and clock networks.

Responsabilités

• Lead PD flows and optimization from block to full-chip.
• Define Synthesis to layout flows, including PDN, clock-trees, PVT corners, and custom cells.
• Execute IP and full-chip design optimizations with PD engineers.
• Deliver tapeout-ready designs optimized for target PPA.

Connaissances

PD flows

Full-chip optimization

Clock trees

Synthesis layout

Outils

ECAD tools

Description du poste

Phinity Labs, an AI research lab in San Francisco, seeks a Physical Design Lead to drive block-to-full-chip PD flows and optimize PPA. You will define synthesis-to-layout flows, PDN, clock trees, and cell characterizations, delivering tapeout-ready designs.

You will collaborate with top researchers and hardware experts, shape strategy, and own high-impact PD initiatives across power, performance, and area trade-offs in cutting-edge accelerator chips.