Lead ASIC Floorplan Engineer - PPA, Tapeout & Equity

Broadcom; Fort Collins (CO); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical/Dental/Vision

401K matching

ESPP

Paid holidays

PTO & leave

Job summary

Broadcom's Custom Silicon Design Team in Fort Collins, CO is seeking a Floorplan Engineer for chip-level physical architecture on advanced ASICs. You will define die layout, partitioning, and top-level floorplanning for AI, networking, and computing SoCs, working across 3 nm and smaller nodes from concept to production.

You will lead timing closure, PPA optimization, and cross-functional integration, mentoring teams and guiding new initiatives. A senior, design-focused background is required.

Qualifications

• BS in Electrical or Computer Engineering with 12+ years of relevant experience, or
• MS in Electrical or Computer Engineering with 10+ years of relevant experience.

Responsibilities

• Define and optimize top-level floorplan architecture, including die size estimation and partitioning.
• Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization.
• Collaborate with RTL, timing, and packaging teams to balance performance, power, and area targets.
• Lead top-level timing closure, congestion analysis, and ECO implementation for tapeout readiness.
• Coordinate with block owners and integration teams for smooth convergence.
• Provide guidance and technical support to internal and external partners.
• Apply understanding of PnR, timing closure, and physical verification to achieve signoff-quality results.
• Contribute to design flow automation for advanced process technologies.

Skills

VLSI design principles

Floorplanning

Partitioning

Clock networks

PPA optimization

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

TCL scripting

Linux environments

Python/Perl/Ruby

Cadence or PD tools

Job description

Broadcom's Custom Silicon Design Team in Fort Collins, CO is seeking a Floorplan Engineer for chip-level physical architecture on advanced ASICs. You will define die layout, partitioning, and top-level floorplanning for AI, networking, and computing SoCs, working across 3 nm and smaller nodes from concept to production.

You will lead timing closure, PPA optimization, and cross-functional integration, mentoring teams and guiding new initiatives. A senior, design-focused background is required.