Senior ASIC Floorplan Engineer for 3nm SoCs

Broadcom, Inc.; Fort Collins (CO); On-site; USD 150,000 - 230,000; Full time

Benefits offered by this job

Medical Insurance

Dental & Vision

401(k) matching

ESPP

Employee Assistance Program

Paid holidays

Paid sick leave

Vacation time

Job summary

Broadcom, Inc. in Fort Collins, Colorado, is seeking a Floorplan Engineer to drive chip-level physical architecture for advanced ASICs beyond 1 GHz. You will shape top-level floorplan, partitioning, and hierarchy across AI, networking, and computing SoCs from concept to production.

Join a world-class design team using 3 nm and smaller nodes, collaborating with RTL, timing, and packaging to optimize PPA and ensure tapeout readiness. Strong TCL scripting, Linux, and Cadence tooling are required.

Qualifications

• BS with 12+ years or MS with 10+ years of relevant ECE experience.
• Strong floorplanning and die partitioning skills.
• Proficiency with TCL scripting and Linux.

Responsibilities

• Define and optimize top-level floorplan architecture, including die size estimation and partitioning.
• Drive macro placement, power grid design, clock distribution planning, pin placement, and feedthrough optimization.
• Collaborate with RTL, timing, and packaging teams to balance performance, power, and area (PPA).
• Lead top-level timing closure, congestion analysis, and ECO implementation to ensure clean tapeout readiness.
• Coordinate with block owners and integration teams for smooth block-level to top-level convergence.
• Support cross-functional design integration and provide guidance to partners.
• Apply deep understanding of PnR, timing closure, physical verification, and IR/EM analysis to achieve signoff-quality results.
• Contribute to design flow automation and methodology development for advanced process technologies.

Skills

VLSI design

Floorplanning

Die partitioning

Clock networks

PPA optimization

TCL scripting

Linux

Cadence

Education

BS in Electrical or Computer Engineering

MS in Electrical or Computer Engineering

Tools

Cadence tools

EDA software

Job description

Broadcom, Inc. in Fort Collins, Colorado, is seeking a Floorplan Engineer to drive chip-level physical architecture for advanced ASICs beyond 1 GHz. You will shape top-level floorplan, partitioning, and hierarchy across AI, networking, and computing SoCs from concept to production.

Join a world-class design team using 3 nm and smaller nodes, collaborating with RTL, timing, and packaging to optimize PPA and ensure tapeout readiness. Strong TCL scripting, Linux, and Cadence tooling are required.