Senior Physical Design Engineer: PPA, Tapeout, Equity

Broadcom; Broomfield (CO); On-site; USD 144,000 - 230,000; Full time

Job summary

Broadcom is seeking an experienced design engineer in Colorado to push place-and-route and timing closure for complex ASIC/SoC designs. The role focuses on floor-planning, partitions, and clock-tree synthesis, with hands-on timing and ECO implementation to meet aggressive PPA targets.

Responsibilities include maintaining flow integrity across 7nm+ process nodes, driving tool use (Primetime, Innovus, ICC2) and collaborating in a global team to deliver Right-first time silicon.

Qualifications

• Primary expertise in place and route and/or timing (constraints, STA) can be considered for this position.
• Hands on experience with timing analysis and place and route tools for ASIC/ SoC Design is a must.
• Experience with formal verification, timing analysis and Eco implementation.
• Full chip tapeout experience based on 7nm and lower technologies is highly preferred.

Responsibilities

• Work on Design Implementation activities related to place and route and/ or timing closure – floor-planning, partitioning, placement, clock tree synthesis, route, timing analysis, timing closure, physical verification (LVS/DRC).
• Drive tools and methodologies to achieve desired PPA metrics.
• Complete equivalence checks, STA, Timing closure and power optimization.
• Implement timing and functional ECOs.
• Apply Broadcom's proven design methodology and milestone flow to meet Broadcom's rigorous criteria for achieving Right-first time silicon.

Skills

Place & route

Timing closure

Design implementation

Floor-planning

Communication skills

Education

BS in Electrical Engineering/ Computer Engineering or related field

MS in Electrical Engineering/ Computer Engineering or related field

Tools

Primetime

ICC2

Innovus

Caliber

LEC

PrimeTime

Job description

Broadcom is seeking an experienced design engineer in Colorado to push place-and-route and timing closure for complex ASIC/SoC designs. The role focuses on floor-planning, partitions, and clock-tree synthesis, with hands-on timing and ECO implementation to meet aggressive PPA targets.

Responsibilities include maintaining flow integrity across 7nm+ process nodes, driving tool use (Primetime, Innovus, ICC2) and collaborating in a global team to deliver Right-first time silicon.