ASIC Design Engineer - High-Speed CMOS & Floorplanning

Broadcom Inc.; Fort Collins (CO); On-site; USD 62,000 - 99,000; Full time

Job summary

Broadcom Inc. ASIC Products Division in Fort Collins, Colorado is seeking an IC design engineer with hands-on experience bringing high-speed CMOS ASICs from concept to product release.

You will manage customer communications, floor planning, routing, timing analysis, physical integration, and rigorous verification of complex high-speed ASICs. The role emphasizes collaboration with cross-functional teams and solving timing, power, and performance challenges to deliver robust designs for AI,

Qualifications

• Bachelor's degree in Electrical Engineering or Computer Engineering is required.
• Legal authorization to work in the U.S. is required.
• Good communication & teamwork skills.
• Self-motivated with the capability to work independently or in a team.

Responsibilities

• Customer communication.
• Floor planning chips and blocks.
• Routing.
• Timing analysis and closure (mission mode and test modes).
• Integration of memories, SerDes, and I/O.
• Work with cross-functional teams.
• Design and verification of complex standard-cell and custom blocks.
• Address power, area, and performance tradeoffs.
• Resolve timing, power integrity and signal integrity issues.
• Physical verification and mask release support.
• Debug complex design issues during and after release.

Skills

Communication

Teamwork

Independence

Self-motivation

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Computer Engineering

Job description

Broadcom Inc. ASIC Products Division in Fort Collins, Colorado is seeking an IC design engineer with hands-on experience bringing high-speed CMOS ASICs from concept to product release.

You will manage customer communications, floor planning, routing, timing analysis, physical integration, and rigorous verification of complex high-speed ASICs. The role emphasizes collaboration with cross-functional teams and solving timing, power, and performance challenges to deliver robust designs for AI,