Lead ASIC Architect - Probabilistic Computing & Tape-out

Energy Jobline CVL; Virginia; On-site; USD 150,000 - 210,000; Full time

Job summary

Energy Jobline CVL in Oxford seeks an experienced ASIC Architect to own architecture from algorithm and ISA definitions to tape-out and silicon bring-up. You will lead HW/SW co-design, model performance, and drive timing/power/area optimizations, collaborating with firmware and compiler teams. The role demands strong RTL and verification strategy expertise and familiarity with Synopsys, Cadence, and Siemens tool flows.

Qualifications

• Proven ownership of ASIC architecture taken to tape-out, ideally in compute accelerators or DSP applications.
• Strong experience in performance modelling, simulation and architectural trade-off analysis using Python, C++ or similar.
• Familiarity with industry-standard semiconductor tool flows (Synopsys, Cadence, Siemens EDA).

Responsibilities

• Own end-to-end ASIC architecture from algorithm/ISA definition through to tape-out and silicon bring-up.
• Define system and ISA, dataflow models based on workload requirements.
• Perform HW/SW co-design, including arithmetic implementation and host interface analysis.
• Build functional simulations and performance models to guide architectural decisions.
• Conduct timing, power and area trade-offs with strong physical design awareness.
• Define microarchitecture specifications including memory hierarchy and interfaces.
• Lead internal IP development and evaluate third-party IP solutions.
• Guide designs through verification, sign-off, tape-out, and silicon bring-up.

Skills

Architectural ownership

Performance modelling

Industry tool flows

Timing/power/area optimisation

HW/SW interfaces

RTL design & verification strategy

Tools

Synopsys Cadence Siemens EDA

Job description

Energy Jobline CVL in Oxford seeks an experienced ASIC Architect to own architecture from algorithm and ISA definitions to tape-out and silicon bring-up. You will lead HW/SW co-design, model performance, and drive timing/power/area optimizations, collaborating with firmware and compiler teams. The role demands strong RTL and verification strategy expertise and familiarity with Synopsys, Cadence, and Siemens tool flows.