Lead ASIC Architect – High-Performance AI Chips (Hybrid)

Cisco Systems, Inc; San Jose (CA); Hybrid; USD 168,000 - 245,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) with Cisco matching

Paid parental leave

Disability coverage

Life insurance

Stock units grants

Job summary

Cisco Systems, Inc. is seeking a senior ASIC verification engineer to drive the definition, architecture and verification of high-performance ASICs in a San Jose environment.

The role involves owning multiple functional areas, developing reusable code, and debugging across ASIC, software, and hardware levels. The candidate will lead DV work, define new verification methodologies, and collaborate with ASIC and apps teams to resolve architectural issues, while contributing to lab bring-up and

Qualifications

• Bachelor's degree with 7+ years related experience, or Master's with 4+ years or PhD with 2+ years.
• Experience with ASIC design and verification processes (with SystemVerilog), debugging, methodology, and tools.

Responsibilities

• Drives the definition, architecture and design and verification of high performance ASICs.
• Owns complex or multiple functional areas.
• Develops reusable code for future projects.
• Creates re-usable code.
• Debugs at ASIC, SW, HW level.
• Leads design and DV work by solving block level issues and participates in chip level issue resolution.

Skills

ASIC design

SystemVerilog

Debugging

Verification methodology

Linux

C/C++

Python/Perl

Education

Bachelor's degree

Master's degree

PhD

Tools

Veloce

Palladium

Zebu

HAPS

Job description

Cisco Systems, Inc. is seeking a senior ASIC verification engineer to drive the definition, architecture and verification of high-performance ASICs in a San Jose environment.

The role involves owning multiple functional areas, developing reusable code, and debugging across ASIC, software, and hardware levels. The candidate will lead DV work, define new verification methodologies, and collaborate with ASIC and apps teams to resolve architectural issues, while contributing to lab bring-up and