Executive ASIC Engineering & Tapeout Leader

Architect Labs; Palo Alto (CA); On-site; USD 300,000 - 600,000; Full time

Benefits offered by this job

Equity

Competitive compensation

Job summary

Architect Labs is seeking a visionary leader to own the ASIC methodology and end-to-end delivery of ambitious AI compute silicons, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. You will build a faster, AI-native flow with data-driven feedback to accelerate design iterations and engineering productivity.

You will lead a world-class team, set uncompromising PPA and silicon quality standards, and personally steer critical technical and execution

Qualifications

• Repeated tapeout success on complex ASIC/SoC programs, ideally at advanced nodes.
• End-to-end ASIC mastery: RTL, verification, synthesis, timing, physical, signoff, bring-up.

Responsibilities

• Own the ASIC methodology and end-to-end delivery from RTL through tapeout.
• Lead a world-class silicon engineering team and drive key technical decisions.
• Push for automation, ML/AI-assisted EDA, and scalable engineering infrastructure.

Skills

ASIC leadership

RTL design

Functional verification

Synthesis

Timing closure

DFT

Team building

Cross-functional leadership

Tools

EDA tools

Automation scripting

Job description

Architect Labs is seeking a visionary leader to own the ASIC methodology and end-to-end delivery of ambitious AI compute silicons, from microarchitecture and RTL through verification, physical design, signoff, and tapeout. You will build a faster, AI-native flow with data-driven feedback to accelerate design iterations and engineering productivity.

You will lead a world-class team, set uncompromising PPA and silicon quality standards, and personally steer critical technical and execution