Lead ASIC Verification Architect – Tape-out Ready

Eridu Corp.; Saratoga (CA); Hybrid; USD 180,000 - 260,000; Full time

Job summary

Eridu Corp. in Silicon Valley seeks a hands-on ASIC Design Verification Lead to own verification strategy and tape-out readiness for high-performance networking silicon. You will drive test plans, build scalable verification environments, and lead cross-functional debug with RTL, architecture, and firmware teams.

The ideal candidate has tape-out experience, deep SystemVerilog/UVM skills, and a pragmatic drive to improve verification quality in a fast-moving startup.

Qualifications

• Strong hands-on experience in ASIC design verification.
• Proven track record of taking at least one complex ASIC to tape-out with direct verification ownership.
• Deep expertise in SystemVerilog and UVM-based verification methodologies.
• Strong understanding of ASIC design and verification flows, including simulation, coverage, and debug.
• Experience with block-level through full-chip verification and integration.
• Ability to drive execution in ambiguous, fast-paced startup environments.
• Excellent communication skills and ability to collaborate across disciplines.

Responsibilities

• Define and own block-, subsystem-, and chip-level verification strategies.
• Develop and maintain scalable verification environments using SystemVerilog and UVM.
• Drive execution from test-plan definition through coverage and bug closure.
• Ensure verification readiness as a gating requirement for tape-out.
• Write and review high-quality testbenches, sequences, checkers, and scoreboards.
• Develop constrained-random, directed, and stress tests to validate complex corner cases.
• Actively debug functional failures across RTL, testbench, and simulation environments.
• Define functional, code, and assertion coverage goals.
• Analyze coverage results and identify verification gaps.
• Provide clear, actionable feedback to RTL designers to improve design and test quality.
• Partner closely with RTL, architecture, physical design, and firmware teams.
• Drive root-cause analysis of functional, performance, and integration issues.
• Support gate-level, timing-aware, and power-aware simulations as required.
• Partner and support emulation and post silicon validation of the ASIC design.
• Lead full-chip verification planning, execution, and closure.
• Support emulation and acceleration environments where appropriate.
• Ensure clean handoff to silicon bring-up teams with high confidence in design correctness.
• Establish and enforce verification checklists and quality gates.
• Track verification progress and risk, proactively escalating issues.
• Lead by technical authority and hands-on contribution rather than coordination alone.
• Continuously improve verification methodology, infrastructure, and best practices.

Skills

ASIC design verification

SystemVerilog

UVM

Tape-out ownership

Debugging

Communication

Tools

SystemVerilog

UVM

Job description

Eridu Corp. in Silicon Valley seeks a hands-on ASIC Design Verification Lead to own verification strategy and tape-out readiness for high-performance networking silicon. You will drive test plans, build scalable verification environments, and lead cross-functional debug with RTL, architecture, and firmware teams.

The ideal candidate has tape-out experience, deep SystemVerilog/UVM skills, and a pragmatic drive to improve verification quality in a fast-moving startup.