ASIC Architect in Oxfordshire

Energy Jobline CVL; Virginia; Vor Ort; USD 150.000 - 210.000; Vollzeit

Zusammenfassung

Energy Jobline CVL in Oxford seeks an experienced ASIC Architect to own architecture from algorithm and ISA definitions to tape-out and silicon bring-up. You will lead HW/SW co-design, model performance, and drive timing/power/area optimizations, collaborating with firmware and compiler teams. The role demands strong RTL and verification strategy expertise and familiarity with Synopsys, Cadence, and Siemens tool flows.

Qualifikationen

• Proven ownership of ASIC architecture taken to tape-out, ideally in compute accelerators or DSP applications.
• Strong experience in performance modelling, simulation and architectural trade-off analysis using Python, C++ or similar.
• Familiarity with industry-standard semiconductor tool flows (Synopsys, Cadence, Siemens EDA).

Aufgaben

• Own end-to-end ASIC architecture from algorithm/ISA definition through to tape-out and silicon bring-up.
• Define system and ISA, dataflow models based on workload requirements.
• Perform HW/SW co-design, including arithmetic implementation and host interface analysis.
• Build functional simulations and performance models to guide architectural decisions.
• Conduct timing, power and area trade-offs with strong physical design awareness.
• Define microarchitecture specifications including memory hierarchy and interfaces.
• Lead internal IP development and evaluate third-party IP solutions.
• Guide designs through verification, sign-off, tape-out, and silicon bring-up.

Kenntnisse

Architectural ownership

Performance modelling

Industry tool flows

Timing/power/area optimisation

HW/SW interfaces

RTL design & verification strategy

Tools

Synopsys Cadence Siemens EDA

Jobbeschreibung

Great opportunity for an experienced ASIC Architect to join an innovative next- computing company and taking ownership of the architecture and development of a cutting-edge probabilistic computing processor. This is a highly influential role where you will lead ASIC architecture from algorithm and ISA definition through to tape-out and silicon bring-up.

Key Responsibilities for the ASIC Architect role based in Oxford:

• Own the end-to-end ASIC architecture of a probabilistic computing processor, from algorithm understanding through to tape-out.
• Define system architecture, instruction set architecture (ISA) and dataflow models based on workload requirements.
• Perform HW/SW co-design activities, including arithmetic implementation and analysis of programmability and host requirements.
• Build functional simulations and performance models to guide architectural decisions.
• Conduct timing, power and area trade-off analysis with strong physical design awareness.
• Define detailed microarchitecture specifications, including memory hierarchy, connectivity and interface requirements.
• Lead internal IP development and evaluate third-party IP solutions.
• Guide designs through verification, sign-off, tape-out and silicon bring-up.

Key Skills Required for the ASIC Architect role based in Oxford:

• Proven architectural ownership of at least one ASIC taken successfully to tape-out, ideally within compute accelerators, inference engines or DSP applications.
• Strong hands-on experience with performance modelling, simulation and architectural trade-off analysis using Python, C++ or similar .
• Experience with industry-standard semiconductor tool flows such as Synopsys, Cadence or Siemens EDA tools.
• Solid understanding of timing, power and area optimisation at the architectural level.
• Experience defining hardware/software interfaces and collaborating with firmware and compiler teams.
• Strong RTL design knowledge and experience defining verification strategies from an architectural perspective.

This is a fantastic opportunity to play a pivotal role in developing revolutionary computing technology, influencing product direction and driving innovation from concept through to silicon deployment.