Lead ASIC Architect for High-Performance Networking SoCs

Cisco Systems; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco Systems’ Silicon One team seeks a senior designer to architect CPU subsystems for next‑gen switch ASICs. You will drive RTL design, pre‑silicon verification, and post‑silicon bring‑up, coordinating with SDK, BSP, and NOS teams to define interfaces and memory models.

You will also work on emulation/FPGA platforms and guide security and boot considerations, with extensive experience in PCIe and interconnect fabrics. This role anchors Cisco’s high‑performance networking portfolio.

Qualifications

• Bachelor’s degree plus 8+ years of related experience (or Master’s 6+ years; PhD 3+ years).
• Experience with microarchitectural RISC-V, ARM or ARC processor ecosystems.
• Experience with on-chip interconnect fabrics (AXI, CHI, NoC).
• Experience with PCIe subsystems.
• Experience with ASIC/SoC design flow and RTL in SystemVerilog, pre-silicon verification, lint, CDC/RDC, synthesis/timing, and post-silicon bring-up.

Responsibilities

• Lead architecture and design of complex CPU subsystems for high-performance networking switch ASICs.
• Collaborate with SDK, BSP, and NOS teams to define driver interfaces, registers and memory models.
• Support early emulation and FPGA platforms throughout development.

Skills

RTL design

SystemVerilog

pre-silicon verification

lint CDC/RDC

synthesis and timing

post-silicon bring-up

PCIe subsystems

ASIC/SoC design flow

CPU/SoC architecture leadership

debug/trace infrastructure

Education

Bachelor’s degree + 8 years related experience

Master’s degree + 6 years related experience

PhD + 3 years related experience

Job description

Cisco Systems’ Silicon One team seeks a senior designer to architect CPU subsystems for next‑gen switch ASICs. You will drive RTL design, pre‑silicon verification, and post‑silicon bring‑up, coordinating with SDK, BSP, and NOS teams to define interfaces and memory models.

You will also work on emulation/FPGA platforms and guide security and boot considerations, with extensive experience in PCIe and interconnect fabrics. This role anchors Cisco’s high‑performance networking portfolio.