Lead ASIC CPU Subsystem Architect – Networking

Hardware FYI; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Job summary

Cisco in San Jose is seeking an experienced designer to lead architecture and design of CPU subsystems for next‑generation high‑performance networking switch ASICs. You will drive the full ASIC development lifecycle from specification and RTL design to post-silicon bring‑up.

You will collaborate with SDK, BSP and Network OS teams to define driver interfaces, register maps and memory models, while enabling early emulation and FPGA platforms.

Qualifications

• Minimum degree requirements with extensive related experience.
• Experience with microarchitectural RISC‑V, ARM or ARC ecosystems.
• Experience with on‑chip interconnect fabrics (AXI/CHI/NoC) and PCIe.
• Experience with ASIC/SoC design flow from RTL to post‑silicon.

Responsibilities

• Lead the architecture and design of CPU subsystems for next‑gen network switch ASICs.
• Collaborate with SDK, BSP, and NOS teams to define driver interfaces and memory models.
• Support early emulation and FPGA platforms during development.
• Oversee RTL design to post‑silicon bring‑up across SoC blocks.

Skills

RISC-V

ARM

ARC

PCIe subsystems

SoC/ASIC design flow

Education

Bachelor’s degree

Master’s degree

PhD

Tools

SystemVerilog

pre-silicon verification

lint

synthesis/timing/constraints

implementation handoff

post-silicon bring-up

Job description

Cisco in San Jose is seeking an experienced designer to lead architecture and design of CPU subsystems for next‑generation high‑performance networking switch ASICs. You will drive the full ASIC development lifecycle from specification and RTL design to post-silicon bring‑up.

You will collaborate with SDK, BSP and Network OS teams to define driver interfaces, register maps and memory models, while enabling early emulation and FPGA platforms.