Senior ASIC Architect - High-Performance CPU Subsystems

020 Cisco Systems, Inc.; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Benefits offered by this job

Medical, dental and vision insurance

401(k) plan with Cisco matching

Paid parental leave

Disability coverage

Life insurance

RSU grants vesting schedule

Paid holidays and vacation time

Floating holiday

Birthday day off

Wellness days/ PTO

Job summary

Cisco Systems, Inc. is seeking a highly experienced designer to lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs.

You will work on RTL design, post-silicon bring-up, and coordinate with SDK, BSP, and NOS teams to define interfaces and memory models. Required are extensive experience with SystemVerilog, pre-silicon verification, and PCIe subsystems, along with leadership in CPU/SoC architecture for data-center networking.

Qualifications

• Bachelor’s + 8 years of related experience, or Master’s + 6 years, or PhD + 3 years.
• Experience with microarchitectural RISC-V, ARM or ARC processor ecosystems.
• Experience with on-chip interconnect fabrics (AXI, CHI, NoC) and PCIe subsystems.

Responsibilities

• Lead architecture and design of CPU subsystems for high-performance networking switch ASICs.
• Collaborate with SDK, BSP, and NOS software teams to define driver interfaces, register maps, and memory models.
• Support early emulation and FPGA platforms.

Skills

RISC-V/ARM/ARC ecosystems

Interconnect fabrics AXI/CHI/NoC

PCIe subsystems

ASIC/SoC design flow

Education

Bachelor's + 8 years / Master +6 years / PhD +3 years

Tools

SystemVerilog RTL

Pre-silicon verification

Lint

CDC/RDC

Synthesis/ timing/ constraints

Job description

Cisco Systems, Inc. is seeking a highly experienced designer to lead the architecture and design of complex CPU subsystems for next-generation high-performance networking switch ASICs.

You will work on RTL design, post-silicon bring-up, and coordinate with SDK, BSP, and NOS teams to define interfaces and memory models. Required are extensive experience with SystemVerilog, pre-silicon verification, and PCIe subsystems, along with leadership in CPU/SoC architecture for data-center networking.